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US 9,602,318 B2Granted
Closed-loop high-speed channel equalizer adaptation
AssigneeTexas Instruments Incorporated
InventorsRoland Sperlich, Huanzhang Huang, Charles M. Branch
Life of this patent
Estimating the term…
Abstract
A serial communication circuit (FIG. 3) is disclosed. The circuit includes an equalizer circuit (306) arranged to receive a data signal (CH 1) and produce an equalized data signal. A log detector circuit (300) receives the data signal and produces a power signal indicating a power level of the data signal. A decision circuit (332) receives the power signal and produces a select signal. A first selection circuit (336) receives a plurality of first correction signals and applies one of the first correction signals to the equalizer circuit in response to the select signal.
Claims23
A circuit comprising:
- an input lead configured to receive a data signal;
- an equalizer circuit coupled with the input lead to receive the data signal, the equalizer circuit configured to equalize the data signal based on a correction signal;
- an equalization filter coupled with the equalizer circuit to receive the equalized data signal, the equalization filter configured to generate the correction signal based on a signal attenuation of the equalized data signal;
- and
- a regulation circuit coupled with the input lead to receive the data signal, and coupled with the equalization filter to receive the correction signal, the regulation circuit configured to selectively deliver or block the correction signal from the equalization filter to the equalizer circuit based on a power level of the data signal received from the input lead.
2 more elements
A circuit comprising:
- an equalizer circuit configured to receive a data signal, the equalizer circuit configured to equalize the data signal based on a correction signal;
- an first filter coupled with the equalizer circuit to receive the equalized data signal, the first filter configured to generate a first correction signal based on a first signal attenuation of the equalized data signal;
- an amplifier circuit coupled with the equalizer circuit to receive the equalized data signal, the amplifier circuit configured to amplify the equalized data signal;
- and
- an second filter coupled with the amplifier circuit to receive the amplified equalized data signal, the second filter configured to generate a second correction signal based on a second signal attenuation of the amplified equalized data signal;
- and
- a regulation circuit coupled with the first and second filters, the regulation circuit configured to generate the correction signal by selecting the first correction signal and the second correction signal based on a power level of the data signal.
4 more elements
A circuit comprising:
- an equalizer circuit configured to receive a data signal, the equalizer circuit configured to equalize the data signal based on a first correction signal;
- an first filter coupled with the equalizer circuit to receive the equalized data signal, the first filter configured to generate the first correction signal based on a first signal attenuation of the equalized data signal;
- an amplifier circuit coupled with the equalizer circuit to receive the equalized data signal, the amplifier circuit configured to amplify the equalized data signal based on a second correction signal;
- and
- an second filter coupled with the amplifier circuit to receive the amplified equalized data signal, the second filter configured to generate the second correction signal based on a second signal attenuation of the amplified equalized data signal;
- and
- a regulation circuit coupled with the first and second filters, the regulation circuit configured to selectively deliver the first correction signal to the equalizer circuit and selectively deliver the second correction signal to the amplifier circuit based on a power level of the data signal.
4 more elements
A circuit comprising:
- an input lead configured to receive a data signal;
- an equalizer circuit coupled with the input lead to receive the data signal, the equalizer circuit configured to equalize the data signal based on a correction signal;
- an equalization filter coupled with the equalizer circuit to receive the equalized data signal, the equalization filter configured to generate the correction signal based on a signal attenuation of the equalized data signal;
- and
- a regulation circuit including:
- a log detector circuit coupled with the input lead to receive the data signal, the log detector circuit configured to generate a power signal representing the power level of the data signal;
- a decision feed forward circuit coupled with the log detector circuit to receive the power signal, the decision feed forward circuit configured to alter a select signal when the power level is below a threshold;
- and
- a selection circuit coupled with the decision feed forward circuit to receive the select signal, and coupled with the equalization filter to receive the correction signal, the selection circuit configured to select the correction signal for delivery to the equalizer circuit based on the select signal.
6 more elements
A circuit comprising:
- an equalizer circuit configured to receive a data signal, the equalizer circuit configured to equalize the data signal based on a correction signal by adjusting a pass characteristic to compensate a first signal attenuation and a second signal attenuation based on the correction signal;
- an first filter coupled with the equalizer circuit to receive the equalized data signal, the first filter configured to:
- sample the equalized data signal to determine the first signal attenuation over a first design bandwidth, and generate a first correction signal based on the first signal attenuation of the equalized data signal;
- an amplifier circuit coupled with the equalizer circuit to receive the equalized data signal, the amplifier circuit configured to amplify the equalized data signal;
- and
- an second filter coupled with the amplifier circuit to receive the amplified equalized data signal, the second filter configured to:
- to sample the amplified equalized data signal to determine the second signal attenuation over a second design bandwidth extending beyond the first design bandwidth, and generate a second correction signal based on the second signal attenuation of the amplified equalized data signal;
- and
- a regulation circuit coupled with the first and second filters, the regulation circuit configured to generate the correction signal by selecting the first correction signal and the second correction signal based on a power level of the data signal.
6 more elements
A circuit comprising:
- an equalizer circuit configured to receive a data signal, the equalizer circuit configured to equalize the data signal based on a first correction signal;
- an first filter coupled with the equalizer circuit to receive the equalized data signal, the first filter configured to generate the first correction signal based on the first signal attenuation of the equalized data signal;
- an amplifier circuit coupled with the equalizer circuit to receive the equalized data signal, the amplifier circuit configured to amplify the equalized data signal based on a second correction signal;
- and
- an second filter coupled with the amplifier circuit to receive the amplified equalized data signal, the second filter configured to generate the second correction signal based on a second signal attenuation of the amplified equalized data signal;
- and
- a regulation circuit coupled with the first and second filters, the regulation circuit configured to selectively deliver the first correction signal to the equalizer circuit and selectively deliver the second correction signal to the amplifier circuit based on a power level of the data signal,
- wherein the first filter is configured to sample the equalized data signal to determine the signal attenuation over a first design bandwidth;
- wherein the equalizer circuit is configured to adjust a pass characteristic to compensate the first signal attenuation based on the selected first correction signal;
- wherein the second filter is configured to sample the amplified equalized data signal to determine the second signal attenuation over a second design bandwidth extending beyond the first design bandwidth;
- and
- wherein the amplifier circuit is configured to adjust an adjustable gain based on the second correction signal to compensate the second signal attenuation.
9 more elements
Dependencies are inferred from the claim text.