Ambipolar vertical field effect transistor

An ambipolar vertical field effect transistor, comprising:

• a gate layer;
• a dielectric surface treatment layer;
• a dielectric layer disposed between the gate layer and the dielectric surface treatment layer;
• a source layer that is electrically percolating and perforated, where the dielectric surface treatment layer is disposed between the source layer and the dielectric layer;
• a drain layer;
• and
• a semiconducting channel layer disposed between the source layer and the drain layer, wherein the semiconducting channel layer is:
• in contact with at least a portion of the source layer and at least a portion of the dielectric surface treatment layer,
• includes at least one first domain of p-type semiconductor material having a HOMO level within 2 eV below a Fermi level of the source layer, and
• includes at least one second domain of n-type semiconductor material having a LUMO level within 2 eV above the Fermi level of the source layer.

An inverter comprising:

• two back-to-back connected ambipolar vertical field effect transistors, wherein a first ambipolar vertical field effect transistor of the two back-to-back connected ambipolar vertical field effect transistors comprises:
• a gate layer;
• a source layer that is electrically percolating and perforated;
• a dielectric layer disposed between the gate layer and the source layer;
• a drain layer;
• and
• a semiconducting channel layer disposed between the source layer and the drain layer, where the semiconducting channel layer is in contact with at least a portion of the source layer and at least a portion of the dielectric layer, and includes at least one p-type semiconductor domain and at least one n-type semiconductor domain, and wherein the drain layer forms a hole injection barrier for the at least one p-type semiconductor domain and an electron injection barrier for the at least one n-type semiconductor domain.