FinFETs with strained well regions

A method comprising:

• forming a semiconductor region having a portion over top surfaces of insulation regions, wherein the semiconductor region comprises:
• a wide portion with opposite sidewalls contacting edges of the insulation regions, wherein the wide portion has a top surface substantially level with top surfaces of the insulation regions;
• and
• a narrow portion narrower than the wide portion over the wide portion, wherein the wide portion comprises an extension portion laterally extending beyond a respective sidewall of the narrow portion, and the narrow portion has a first bandgap;
• epitaxially growing a semiconductor layer contacting a top surface and sidewalls of the narrow portion, wherein the semiconductor layer has a second bandgap greater than the first bandgap;
• and
• forming a gate stack overlapping both the narrow portion and the extension portion of the wide portion.

A method comprising:

• recessing a portion of a substrate between two insulation regions to form a recess;
• performing a first epitaxy to grow a first semiconductor region in the recess, wherein the first semiconductor region is relaxed;
• performing a second epitaxy to grow a second semiconductor region in the recess, wherein the second semiconductor region is over and contacting the first semiconductor region, and wherein the second semiconductor region has a tensile strain;
• performing a planarization to level a top surface of the second semiconductor region and the insulation regions;
• recessing the insulation regions, wherein a top portion of the second semiconductor region higher than the insulation regions forms a semiconductor fin;
• thinning the semiconductor fin;
• and
• performing a third epitaxy to grow a third semiconductor region on a top surface and sidewalls of the semiconductor fin, wherein the second semiconductor region has a conduction band lower than conduction bands of the first and the third semiconductor regions.