US 9,595,971 B2 · Ring frequency divider

Abstract

A circuit for a divider or counter may include a frequency divider having multiple rings for dividing an input frequency to obtain an output frequency. The first and second rings may include an odd-numbered plurality of elements, such as inverters, wherein each inverter of a ring is coupled to another inverter of the ring in a circular chain. An input frequency may be input to a power supply input of inverters of the first ring. The second ring inverters may be coupled at a power supply input to output nodes of the first ring inverters, which results in the second ring operating at a divisional rate of the first frequency given by (N−1), where N is the number of inverters in the ring. The circuits may be used in frequency dividers and counters, such as in phase-locked loops (PLLs) and analog-to-digital converters (ADCs).

Claims29

Dependent claims

A ring divider, comprising:

a first master ring oscillator configured to oscillate at a first frequency determined by an applied signal;
and
a second slave ring oscillator interconnected to the first ring oscillator, wherein the second ring oscillator is configured by the interconnection with the first ring oscillator to operate at a second frequency that is the first frequency divided by an integer.

An analog-to-digital converter (ADC), comprising:

an input node configured to receive an input analog signal;
a current-controlled oscillator configured to receive the input analog signal, the current-controlled oscillator comprising:
a first master ring oscillator configured to be driven at a first frequency determined by the input analog signal;
and
a second slave ring oscillator interconnected to the first ring oscillator, wherein the second ring oscillator is configured by the interconnection with the first ring oscillator to operate at a second frequency that is the first frequency divided by an integer such that the second ring oscillator and the first ring oscillator form a ring divider,
wherein the first ring oscillator comprises a first plurality of latches configured in a chain such that an input of each of the plurality of latches is an output of a different one of the first plurality of latches, and wherein the second ring oscillator comprises a second plurality of latches configured in a chain such that an input of each of the second plurality of latches is an output of a different one of the second plurality of latches;
and
a decoder coupled to an output of the current-controlled oscillator and configured to output digital bits representing the input analog signal.

5 more elements

A phase-locked loop (PLL) system, comprising:

an input node configured to receive an input signal of a first frequency;
a phase frequency detector coupled to the input node;
a charge pump coupled to the phase frequency detector;
a low-pass filter coupled to the charge pump;
a voltage-controlled oscillator configured to receive an output of the low-pass filter, the voltage-controlled oscillator comprising:
a first master ring oscillator configured to be driven at a first frequency determined by the low-pass filter;
and
a second slave ring oscillator interconnected to the first ring oscillator, wherein the second ring oscillator is configured by the interconnection with the first ring oscillator to operate at a second frequency that is the first frequency divided by an integer such that the second ring oscillator and the first ring oscillator form a ring divider, wherein an output of the second ring oscillator is coupled to the phase frequency detector,
wherein the first ring oscillator comprises a first plurality of latches configured in a chain such that an input of each of the plurality of latches is an output of a different one of the first plurality of latches, and wherein the second ring oscillator comprises a second plurality of latches configured in a chain such that an input of each of the second plurality of latches is an output of a different one of the second plurality of latches;
and
an output node coupled to the first ring oscillator of the voltage-controlled oscillator and configured to generate an output signal of a second frequency that is an integer multiple of the first frequency.

8 more elements

Dependencies are inferred from the claim text.

Ring frequency divider

Life of this patent

Ring frequency divider

Life of this patent

Abstract

Claims29