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US 9,595,530 B1Granted
Methods and apparatus for vertical bit line structures in three-dimensional nonvolatile memory
AssigneeSanDisk Technologies LLC
InventorGuangle Zhou
Life of this patent
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Abstract
A method is provided that includes forming a first vertical bit line disposed in a first direction above a substrate, forming a first word line disposed in a second direction above the substrate, the second direction perpendicular to the first direction, forming a first memory cell comprising a nonvolatile memory material at an intersection of the first vertical bit line and the first word line, forming a transistor above the substrate, and forming a first bit line select device coupled between the first vertical bit line and the transistor.
Claims20
A method comprising:
- forming a first vertical bit line disposed in a first direction above a substrate;
- forming a first word line disposed in a second direction above the substrate, the second direction perpendicular to the first direction;
- forming a first memory cell comprising a nonvolatile memory material at an intersection of the first vertical bit line and the first word line;
- forming a transistor above the substrate;
- and
- forming a first bit line select device coupled between the first vertical bit line and the transistor.
3 more elements
A method comprising:
- forming a plurality of vertical bit lines disposed in a first direction above a substrate;
- forming a plurality of first word lines disposed in a second direction above the substrate, the second direction perpendicular to the first direction;
- forming a first memory level comprising a plurality of memory cells, each memory cell comprising a nonvolatile memory material disposed at an intersection of one of the vertical bit lines and a corresponding one of the first word lines;
- and
- forming a plurality of transistors above the substrate, each of the transistors coupled to a corresponding two of the vertical bit lines,
- wherein each of the vertical bit lines is coupled to only one memory cell on the first memory level.
3 more elements
An apparatus comprising:
- a monolithic three-dimensional memory array comprising:
- a vertical bit line disposed in a first direction above a substrate;
- a word line disposed in a second direction above the substrate, the second direction perpendicular to the first direction;
- a memory cell comprising a nonvolatile memory material at an intersection of the vertical bit line and the word line;
- a transistor above the substrate;
- and
- a bit line select device coupled between the vertical bit line and the transistor, wherein the bit line select devices comprises any of a gated resistor and a junctionless transistor.
4 more elements
Dependencies are inferred from the claim text.