US 9,590,089 B2 · Variable gate width for gate all-around transistors

Abstract

Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to fabricate such devices are also described. One or more embodiments of the present invention are directed at approaches for varying the gate width of a transistor structure comprising a nanowire stack having a distinct number of nanowires. The approaches include rendering a certain number of nanowires inactive (i.e. so that current does not flow through the nanowire), by severing the channel region, burying the source and drain regions, or both. Overall, the gate width of nanowire-based structures having a plurality of nanowires may be varied by rendering a certain number of nanowires inactive, while maintaining other nanowires as active.

Claims16

Dependent claims

A semiconductor device, comprising:

a plurality of vertically stacked nanowires disposed above a substrate, each of the plurality of vertically stacked nanowires formed of a same semiconductor material wherein one of the nanowires of the plurality of vertically stacked nanowires is an active nanowire and wherein one of the nanowires of the plurality of vertically stacked nanowires is an inactive nanowire, wherein the same semiconductor material of the inactive nanowire is severed in the channel region of the inactive nanowire;
a gate structure wrapped around the active nanowire, defining a channel region of the device;
and
a source region and a drain region on opposite sides of the channel region.

1 more element

Dependencies are inferred from the claim text.

Variable gate width for gate all-around transistors

Life of this patent

Variable gate width for gate all-around transistors

Life of this patent

Abstract

Claims16