Packaging solutions for devices and systems comprising lateral GaN power transistors

A method of fabricating a semiconductor device structure comprising an assembly of a lateral GaN power transistor fabricated on a semiconductor substrate (GaN die) and packaging components comprising a leadframe and a substrate, the method comprising:

• providing the GaN die comprising, on a front surface thereof, source, drain and gate contact areas for the lateral GaN power transistor and a back surface thereof for die-attach;
• providing the leadframe of copper, or another metal or metal alloy having a high electrical conductivity, the leadframe being patterned to provide source, drain and gate portions corresponding to source, drain and gate contact areas on the front surface of the GaN die;
• attaching the source, drain and gate contact areas of the GaN die with electrical interconnections connected to respective source, drain and gate portions of one side of the copper leadframe, comprising low inductance bump or post connections, to form an interposer sub-assembly;
• source, drain and gate leads of the leadframe extending laterally and vertically of the GaN die to provide source, drain and gate leads providing contact surfaces coplanar with the die-attach surface of the GaN die for electrical interconnection to respective coplanar contact areas of the substrate;
• and
• providing a layer of soldered or sintered material which is electrically and thermally conductive to attach the back-side surface of the GaN die to the die-attach area of the substrate, and to electrically interconnect the respective source, drain and gate interconnections of the leadframe and substrate contact areas.