Circular time differencing add/subtract delta to TMAX on sign, MSB
AssigneeTexas Instruments Incorporated
InventorAndrew W. Welin
Life of this patent
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Abstract
A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing of the packets according to the respective deadline intervals. A single-chip integrated circuit has a processor circuit and embedded electronic instructions forming an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that extract a packet deadline intervals, place packets in the egress scheduling list according to deadline intervals; and embed a decoder that decodes the packets according to a priority depending to their deadline intervals.
Claims14
A process of generating circular time differences between times of events A and B in an integrated circuit comprising:
- electronically subtracting in an adder/subtractor circuit and delivering to a register a value representative of the time of event B from a value representative of the time of event A, resulting in an electronic representation (delta) having a most significant bit (MSB) and a sign bit S;
- and
- electronically processing in logic circuitry the electronic representation (delta) and a predetermined value (TMAX) in response to the MSB and the sign bit S to generate the circular time difference, the electronically processing in the logic circuitry includes adding the electronic representation (delta) to the value (TMAX) provided the sign bit is positive and the MSB is zero.
A single-chip circular time differencing integrated circuit comprising:
- storage for values representative of the time of two events;
- an adder/subtractor coupled to the storage and operative to generate an electronic difference (delta) and deliver the difference value into the storage of a sign bit (S) and a most significant bit (MSB) of the difference value (delta);
- and
- logic circuitry responsive to the MSB and the sign bit S of the electronic difference (delta) and a predetermined value (TMAX), the logic circuitry driving the adder/subtractor to generate the circular time difference of the two events, the logic circuitry driving the adder/subtractor to add the electronic representation (delta) to the predetermined value (TMAX) provided the sign bit is positive and the MSB is zero and to subtract the redetermined value TMAX from the electronic representation delta when the sign bit is positive and the MSB is one.
A process of generating circular time differences between times of events A and B in an integrated circuit comprising:
- electronically subtracting in an adder/subtractor circuit and delivering to a register a value representative of the time of event B from a value representative of the time of event A, resulting in an electronic representation (delta) having a most significant bit (MSB) and a sign bit S;
- and
- electronically processing in logic circuitry the electronic representation (delta) and a predetermined value (TMAX) in response to the MSB and the sign bit S to generate the circular time difference, the electronically processing in the logic circuitry includes subtracting the predetermined value (TMAX) from the electronic representation (delta) when the sign bit is positive and the MSB is one.
Dependencies are inferred from the claim text.