Delta sigma patterns for calibrating a digital-to-analog converter
AssigneeAnalog Devices, Inc.
InventorMartin Clara
Life of this patent
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Abstract
A digital to analog converter (DAC) maps a digital word to an analog output. The DAC bits may have amplitude and timing errors. These errors (or sometimes referred herein as “non-idealities”) result in distortion and degradation of the dynamic range in DACs. To reduce these negative effects, delta-sigma patterns can be provided to two bit cells, a reference bit cell and a bit cell under calibration, to perform, e.g., amplitude calibration and timing skew calibration. Delta-sigma patterns are particularly advantageous over square wave signals, which cannot be scaled to perform amplitude calibration between bit cells having different bit weights and are limited in frequency to integer fractions of the sampling clock.
Claims21
A method for measuring non-idealities of a digital-to-analog converter (DAC) having a plurality of DAC cells whose outputs are summed to generate an analog output of the DAC, the method comprising:
- generating a first test signal corresponding to a weight of a first DAC cell and a second test signal corresponding to a weight of a second DAC cell;
- encoding the first test signal and the second test signal into a first test input signal and a second test input signal respectively;
- and
- providing the first test input signal and the second test input signal to the first DAC cell and the second DAC cell.
A system for measuring non-idealities of a digital-to-analog converter (DAC) having a plurality of DAC cells whose outputs are summed to generate an analog output of the DAC, the system comprising:
- a test signal generator to scale a test signal with a first multiplicative factor and to scale the test signal with a second multiplicative factor to generate a first test signal and a second test signal respectively;
- a first noise shaper to process the first test signal and generate a first test input signal;
- and
- a second noise shaper to process the second test signal and generate a second test input signal;
- wherein the first test input signal and the second test input signal are provided as input to a first DAC cell and a second DAC cell.
A digital-to-analog converter (DAC) comprising:
- first DAC cell for generating a first analog output based on a first two-level input;
- second DAC cell for generating a second analog output based on a second two-level input;
- means for digitally generating the first two-level input and the second two-level input based on a test signal;
- and
- means for sensing an error of the second DAC cell with respect to the first DAC cell in the analog output of the DAC.
A method for measuring non-idealities of a digital-to-analog converter (DAC) having a plurality of DAC cells whose outputs are summed to generate an analog output of the DAC, the method comprising:
- receiving a first test input signal by a first DAC cell;
- receiving a second test input signal by a second DAC cell, wherein the first test input signal and the second test input signal are encoded and generated based on a weight of the first DAC cell and a weight of the second DAC cell;
- and
- measuring an error of the second DAC cell with respect to the first DAC cell based on outputs of the first DAC cell and the second DAC cell.
Dependencies are inferred from the claim text.