Gate pulsing gate ladder

A gate pulsing bias circuit comprising:

• a resistor ladder comprising a plurality of resistors electrically connected in series;
• a gate enable voltage source electrically connected to a first resistor of the plurality of resistors at a first end of the resistor ladder;
• a first electrical node between the first resistor and a second resistor of the plurality of resistors, the second resistor directly adjacent to the first resistor;
• a field effect transistor (FET), a gate electrode of the FET being electrically connected to the first electrical node;
• a plurality of bond pads, each bond pad of the plurality of bond pads being electrically connected to a corresponding electrical node located between two adjacent resistors of the resistor ladder, wherein there is at least one resistor of the plurality of resistors electrically connected in series between any one of the bond pads and the first electrical node;
• a power supply configured to supply a constant voltage level to a selected one of the plurality of bond pads;
• wherein the gate enable voltage source is configured to produce a first voltage level that places the FET in a conducting state and a second voltage level that places the FET in a non-conducting state.

A method of gate pulsing a field effect transistor (FET) comprising the steps of:

• connecting a gate electrode of said FET to an electrical node between a first resistor and a second resistor of a resistor ladder, the resistor ladder comprising a plurality of resistors electrically connected in series;
• connecting a plurality of bond pads to said resistor ladder at positions, such that at least one resistor of the plurality of resistors is located between each bond pad of the plurality of bond pads;
• connecting a constant voltage supply to a selected bond pad of the plurality of bond pads;
• and
• connecting a gate enable voltage source to the first resistor of said resistor ladder, opposite said electrical node.