US 9,576,094 B2Granted

Logic circuit and system and computer program product for logic synthesis

AssigneesTaiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University

InventorsChi-Chuan Chuang, Yi-Hsiang Lai, Jie-Hong Chiang

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Abstract

A logic circuit includes first and second input, an output, an input acknowledgement node, an output acknowledgement node, a logic evaluation block, a pre-charging circuit, and a completion detection circuit. The logic evaluation block performs a logic evaluation of first and second input signals at the first and second inputs, and to output an output signal corresponding to the logic evaluation. The pre-charging circuit pre-charges the logic evaluation block in response to the first input signal and an acknowledgement signal at the input acknowledgement node. The completion detection circuit generates an acknowledgement signal at the output acknowledgement node in response to the second input signal and the output signal.

Claims20

Dependent claims

A logic circuit, comprising:

at least one first input;
at least one second input;
an output;
an input acknowledgement node configured to be coupled to a next logic stage;
an output acknowledgement node configured to be coupled to a previous logic stage;
a logic evaluation block coupled to the at least one first input, the at least one second input, and the output,
the logic evaluation block configured to perform a logic evaluation of first and second input signals at the corresponding at least one first input and at least one second input, and to output an output signal corresponding to a result of the logic evaluation;
a pre-charging circuit coupled to the at least one first input, the input acknowledgement node, and the logic evaluation block,
the pre-charging circuit configured to pre-charge the logic evaluation block in response to the first input signal and a next stage acknowledgement signal at the input acknowledgement node;
and
a completion detection circuit coupled to the at least one second input, the output, and the output acknowledgement node,
the completion detection circuit configured to generate a previous stage acknowledgement signal at the output acknowledgement node in response to the second input signal and the output signal.

9 more elements

A logic circuit, comprising:

an input acknowledgement node configured to be coupled to a next logic stage;
an output acknowledgement node configured to be coupled to a previous logic stage;
a pre-charging circuit coupled to the input acknowledgement node and a logic evaluation block, the pre-charging circuit configured to pre-charge the logic evaluation block in response to a first input signal and a next stage acknowledgement signal at the input acknowledgement node;
and
a completion detection circuit coupled to the output acknowledgement node,
the completion detection circuit configured to generate a previous stage acknowledgement signal at the output acknowledgement node in response to a second input signal and an output signal, wherein the completion detection circuit comprises a transistor string of serially connected first through fourth transistors, the transistor string having opposite first and second ends, the first end of the transistor string coupled to a first power supply node, the second end of the transistor string coupled to the output acknowledgement node.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/464,366Filed 20 Aug 2014
Published: US 2016/0055270 A125 Feb 2016
Granted: 21 Feb 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/33
Circuit design at the digital level: design verification, e.g. functional simulation or model checking
G06F 30/3312
Using simulation: timing analysis
G06F 30/3323
Design verification, e.g. functional simulation or model checking: using formal methods, e.g. equivalence checking or property checking