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US 9,571,070 B2Granted
Clock circuit for a microprocessor
AssigneeBlackBerry Limited
InventorsMark A. J. Carragher, John William Wynen
Life of this patent
Estimating the term…
Abstract
A mobile communication device includes an analog clock and a digital clock circuit. The analog clock circuit is configured to generate an oscillating output. The digital clock circuit is configured to generate a digital clock output having a frequency that is substantially equal to the frequency of the oscillating output.
Claims17
An electronic device comprising:
- a clock circuit configured to generate a first clock output;
- a frequency divider configured to generate a second clock output by frequency dividing a timing signal;
- a controller configured to:
- in response to a clock select signal being in a first state, enable the first clock output as a clock signal;
- and
- in response to the clock select signal changing from the first state to a second state:
- wait for an edge of the first clock output,
- upon occurrence of the edge of the first clock output, wait for an edge of the timing signal, and
- upon occurrence of the edge of the timing signal, switch from the first clock output being enabled as the clock signal to the second clock output being enabled as the clock signal,
- wherein the enabling is by the controller enabling a selected one of the circuits when disabling the other clock circuit.
7 more elements
A method performed by an electronic device, the method comprising:
- generating, by a first clock circuit, a first clock output;
- generating, by a second clock circuit, a second clock output by frequency dividing a timing signal;
- in response to a clock select signal being in a first state, a controller enabling the first clock output as a clock signal;
- and
- in response to the clock select signal changing from the first state to a second state:
- the controller waiting for an edge of the first clock output,
- upon occurrence of the edge of the first clock output, the controller waiting for an edge of the timing signal, and
- upon occurrence of the edge of the timing signal, the controller switching from the first clock output being enabled as the clock signal to the second clock output being enabled as the clock signal,
- wherein each of the enabling of the first clock output and the enabling of the second clock output is by the controller enabling a selected one of the circuits when disabling the other circuit.
6 more elements
Dependencies are inferred from the claim text.