US 9,570,683 B1Granted

Three-dimensional two-terminal memory with enhanced electric field and segmented interconnects

AssigneeCrossbar, Inc.

InventorsSung Hyun Jo, Kuk-Hwan Kim, Joanna Bettinger

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Abstract

Providing for three-dimensional memory cells having enhanced electric field characteristics and/or memory cells located at broken interconnects is described herein. By way of example, a two-terminal memory cell can be constructed from a layered stack of materials, where respective layers are arranged along a direction that forms a non-zero angle to a normal direction of a substrate surface upon which the layered stack of materials is constructed. In some aspects, the direction can be orthogonal to or substantially orthogonal to the normal direction. In other aspects, the direction can be less than orthogonal to the normal direction. Where an internal angle of the memory cell forms a non-orthogonal angle, an enhanced electric field or current density can result, providing improved switching times and memory performance.

Claims20

Dependent claims

A semiconductor device, comprising:

a first insulating layer formed above a complementary metal oxide semiconductor (CMOS) substrate that comprises a plurality of CMOS devices;
a bottom electrode disposed above the first insulating layer, wherein the bottom electrode comprises a top surface and a bottom surface that are substantially orthogonal to a normal direction of the CMOS substrate, wherein the bottom electrode comprises a third surface coupled to the first surface and the second surface, and wherein the third surface is oblique relative to the normal direction of the CMOS substrate;
a second insulating layer disposed at least in part over the bottom electrode having a via formed therein, wherein at least the third surface of the bottom electrode is exposed by the via;
a switching memory structure disposed within the via and on top of the third surface;
and
a top electrode disposed within the via and on top of the switching memory structure, wherein an electrode material of the top electrode is configured to be ionized and form ions in response to an applied bias across the bottom electrode and the top electrode;
wherein the switching memory structure comprises a switching material, wherein the switching material is permeable to the ions of the top electrode, and wherein the switching material facilitates formation of a conductive path from the ions of the top electrode from the top electrode towards the bottom electrode along a direction that is oblique to the normal direction of the CMOS substrate;
wherein the top electrode, the switching memory structure and the bottom electrode form a memory device;
wherein the bottom electrode layer forms a bitline of the memory device;
and
wherein the top electrode layer forms a wordline of the memory device.

8 more elements

A method for fabricating a semiconductor device, comprising:

receiving a complementary metal oxide semiconductor (CMOS) substrate having a plurality of CMOS devices formed therein;
forming a first insulating layer above the CMOS substrate;
forming a bottom electrode above the first insulating layer, wherein the bottom electrode comprises a top surface and a bottom surface that are substantially orthogonal to a normal direction of the CMOS substrate;
forming a second insulating layer above the bottom electrode;
forming a via within the second insulating layer and within the bottom electrode, wherein a third surface of the bottom electrode is exposed, wherein third surface is coupled to the first surface and the second surface, and wherein the third surface is oblique relative to the normal direction of the CMOS substrate;
forming a switching memory structure within the via, wherein at least a portion the switching memory structure is in contact with the third surface;
and
forming a top electrode within the via, wherein at least a portion of the top electrode is in contact with the portion of the switching memory structure, wherein an electrode material of the top electrode is configured to be ionized and form ions in response to an applied bias across the bottom electrode and the top electrode;
wherein the switching memory structure comprises a switching material, wherein the switching material is permeable to the ions of the top electrode, and wherein the switching material facilitates formation of a conductive path from the ions of the top electrode from the top electrode towards the bottom electrode along a direction that is oblique to the normal direction of the CMOS substrate;
wherein the top electrode, the switching memory structure and the bottom electrode form a memory device;
wherein the bottom electrode layer forms a bitline of the memory device;
and
wherein the top electrode layer forms a wordline of the memory device.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/046,172Filed 17 Feb 2016 · continuation
Priority: 30 Jun 2011
Granted: 14 Feb 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification23 codes

H10N 70/021
Manufacture or treatment of multistable switching devices: formation of switching materials, e.g. deposition of layers
G11C 5/06
Details of stores covered by group G11C11/00: arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 13/0002
Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00: using resistive RAM [RRAM]…
G11C 13/0004
Using resistive RAM [RRAM] elements: comprising amorphous/crystalline phase transition cells

Family

Application61/503,477Us provisional application · filed 30 Jun 2011
Application61/620,561Us provisional application · filed 5 Apr 2012
Application13/525,096Parent of this continuation-in-part · filed 15 Jun 2012
Application13/585,759Parent of this continuation-in-part · filed 14 Aug 2012
Application13/586,815Parent of this continuation-in-part · filed 15 Aug 2012
Application61/712,171Us provisional application · filed 10 Oct 2012
Application61/786,100Us provisional application · filed 14 Mar 2013
Application61/786,058Us provisional application · filed 8 May 2013
Application13/912,136Parent of this continuation-in-part · filed 6 Jun 2013
Application61/859,090Us provisional application · filed 26 Jul 2013
Application14/027,045Parent of this continuation-in-part · filed 13 Sep 2013
Application61/937,417Us provisional application · filed 7 Feb 2014
Application14/194,499Parent of this continuation-in-part · filed 28 Feb 2014
Application14/588,202Parent of this continuation · filed 31 Dec 2014
Application14/588,202Parent of this continuation-in-part
US 9,166,163 B2Parent of this continuation-in-part
US 9,058,865 B1Parent of this continuation-in-part
US 8,946,669 B1Parent of this continuation-in-part
US 8,569,172 B1Parent of this continuation-in-part
US 9,209,396 B2Parent of this continuation-in-part
US 2014/0145135 A1Published application
US 2014/0312296 A1Published application
US 2014/0335675 A1Published application
US 9,564,587 B1Related patent
US 9,627,443 B2Related patent
US 9,570,683 B1This patent

From the US filing history. Foreign family members aren’t listed.