Projection patterning with exposure mask
AssigneesTaiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
InventorsKuen-Yu Tsai, Miin-Jang Chen, Si-Chen Lee
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Abstract
A process for fabricating an integrated circuit is provided. The process includes providing a substrate and forming a hard mask on the substrate. The hard mask may be formed by atomic-layer deposition (ALD) or molecular-layer deposition (MLD). The process also includes disposing an exposure mask over the hard mask and exposing the exposure mask to a patterning particle to pattern a gap in the hard mask. The patterning particle may be, for example, a photon or a charged particle.
Claims20
A process for fabricating an integrated circuit, comprising:
- providing a substrate;
- forming a hard mask on the substrate by one of atomic-layer deposition and molecular-layer deposition;
- disposing an exposure mask over the hard mask;
- and
- exposing the exposure mask to a patterning particle to pattern a gap in the hard mask, the exposing removing at least a portion of the hard mask.
A process for fabricating an integrated circuit, comprising:
- providing a substrate;
- forming a hard mask on the substrate by one of atomic-layer deposition and molecular-layer deposition;
- and
- patterning the hard mask in accordance with an exposure mask, the patterning exposing a portion of the hard mask to a patterning particle.
A process for fabricating an integrated circuit, comprising:
- providing a substrate;
- forming a hard mask on the substrate by one of atomic-layer deposition and molecular-layer deposition;
- disposing an exposure mask over the hard mask;
- flowing a precursor gas over an entire surface of the hard mask;
- and
- exposing a portion of the hard mask to a patterning particle in accordance with the exposure mask to pattern the hard mask, wherein the patterning particle and the precursor gas form a structure on the hard mask.
Dependencies are inferred from the claim text.