Multiple gate field-effect transistors having oxygen-scavenged gate stack
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYee-Chia Yeo, Chih Chieh Yeh, Chih-Hsin Ko, Cheng-Hsien Wu, Liang-Yin Chen, Xiong-Fei Yu, Yen-Ming Chen, Chan-Lon Yang
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Abstract
A method includes forming a silicon cap layer on a semiconductor fin, forming an interfacial layer over the silicon cap layer, forming a high-k gate dielectric over the interfacial layer, and forming a scavenging metal layer over the high-k gate dielectric. An anneal is then performed on the silicon cap layer, the interfacial layer, the high-k gate dielectric, and the scavenging metal layer. A filling metal is deposited over the high-k gate dielectric.
Claims20
A method comprising:
- forming a silicon cap layer on a semiconductor fin;
- forming an interfacial layer over the silicon cap layer;
- forming a high-k gate dielectric over the interfacial layer;
- forming a scavenging metal layer over the high-k gate dielectric;
- performing an anneal on the silicon cap layer, the interfacial layer, the high-k gate dielectric, and the scavenging metal layer;
- and
- depositing a filling metal over the high-k gate dielectric.
A method comprising:
- forming a crystalline silicon cap layer on a silicon germanium fin;
- forming a silicon oxide layer over the crystalline silicon cap layer;
- forming a high-k gate dielectric over the silicon oxide layer;
- forming a scavenging metal layer over the high-k gate dielectric;
- scavenging oxygen from a bottom portion of the silicon oxide layer to convert the bottom portion into a silicon layer, with the silicon layer continuously joined with the crystalline silicon cap layer;
- and
- after the scavenging, depositing a filling metal over the high-k gate dielectric.
A method comprising:
- forming a dummy gate stack on a middle portion of a silicon germanium fin;
- forming source/drain regions on opposite sides of the silicon germanium fin;
- forming an inter-layer dielectric over the source/drain regions, with the dummy gate stack in the inter-layer dielectric;
- removing the dummy gate stack to form a recess in the inter-layer dielectric;
- epitaxially growing a silicon cap layer in the recess, with the silicon cap layer being on the silicon germanium fin;
- depositing a silicon oxide layer over and contacting the silicon cap layer;
- forming a high-k gate dielectric over the silicon oxide layer;
- forming a scavenging metal layer over the high-k gate dielectric, wherein the scavenging metal layer has a first affinity for oxygen higher than a second affinity of a metal in the high-k gate dielectric and a third affinity of silicon;
- performing an anneal to scavenge oxygen from at least a bottom portion of the silicon oxide layer to convert the bottom portion into a silicon layer;
- and
- after the anneal, filling a metal into the recess.
Dependencies are inferred from the claim text.