Six-transistor SRAM semiconductor structures and methods of fabrication
AssigneeKilopass Technology, Inc.
InventorsHarry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng, Christophe J. Chevallier
Life of this patent
Estimating the term…
Abstract
A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.
Claims13
A process for forming an integrated circuit having field effect transistors and having a static random access memory cell which includes a first pair of vertical cross-coupled PNP and NPN bipolar transistors in a first selected region of a first conductivity type semiconductor substrate, and includes a first access transistor outside the first selected region coupled to the pair of vertical cross-coupled PNP and NPN bipolar transistors, the process comprising:
- (a) introducing opposite conductivity type dopant into the selected region of the first conductivity type substrate to form a buried layer;
- (b) introducing first conductivity type dopant into the selected region of the substrate above the buried layer;
- (c) introducing additional opposite conductivity type dopant into a first portion of the selected region to form a shallow well vertically separated from the buried layer by the first conductivity type dopant;
- (d) forming a plurality of gate electrodes for the field effect transistors outside the selected region and simultaneously forming a first gate disposed over only a portion of the shallow well and a second gate disposed entirely over the shallow well;
- using the first gate and the second gate to mask underlying portions of the selected region, performing steps of:
- (e) introducing further first conductivity type dopant into the selected region on opposite sides of the first gate to thereby form a first doped region on one side of the first gate, and a second doped region on an opposing side of the first gate, the opposing side of the first gate being between the first gate and the second gate;
- (f) introducing more opposite conductivity type dopant into the selected region on only one side of the second gate, the only one side being on an opposite side from the opposing side, to thereby form a third doped region;
- (g) providing first electrical connections to interconnect the first pair of vertical cross-coupled PNP and NPN bipolar transistors with each other, and to connect the first access transistor to the first pair of vertical cross-coupled PNP and NPN bipolar transistors.
Dependencies are inferred from the claim text.