OS bypass inter-processor interrupt delivery mechanism

A system for delivering inter-processor interrupts, comprising:

• one or more CPU cores;
• and
• a hardware device in communication with the one or more CPU cores, the hardware device comprising:
• a memory storing a number of context registers, each context register being mapped to an address associated with a particular guest process from a plurality of guest processes executing on the system;
• and
• one or more processors coupled to the memory, the one or more processors being configured to detect when interrupt information is recorded in a given context register associated with a first guest process of the plurality of guess processes, the interrupt information being directed to a second guess process associated with a particular CPU core of the one or more CPU cores,
• wherein in response to detecting that the interrupt information is recorded in the given context register, the one or more processors are configured to generate an interrupt based on the interrupt information that causes the second guest process to run on a different CPU core of the one or more CPU cores without making an operating system call.

A method for delivering inter-processor interrupts, comprising:

• receiving, using one or more processors, interrupt information at a memory space of a hardware device, the memory space being associated with a first guest process;
• identifying, using the one or more processors, a second guest process associated with a particular CPU core based on the interrupt information, the interrupt information including an identifier representing a location associated with the second guest process;
• and
• in response to identifying the second guest process, generating, using the one or more processors, an interrupt directed at the second guest process, the interrupt causing the second guest process to run on a different CPU core without making an operating system call.