Fast process flow, on-wafer interconnection and singulation for MEPV

A method comprising:

• providing an interconnect to a device of a first circuit cell on a substrate and to a device of a second circuit cell on the substrate;
• forming a dielectric layer on the interconnect;
• exposing at least one contact point on the interconnect through the dielectric layer;
• and
• forming at least one opening in the dielectric layer between the first circuit cell and the second circuit cell,
• wherein the interconnect is electrically connected to the first circuit cell and the second circuit cell, and
• wherein the interconnect lies across a boundary between the first circuit cell and the second circuit cell.

A method comprising:

• providing a device layer, wherein the device layer comprises a plurality of device cells;
• depositing a first dielectric layer over the device layer;
• depositing a metal interconnect over the first dielectric layer, wherein the metal interconnect is electrically connected to at least two device cells of the plurality of device cells, and wherein the metal interconnect lies across a boundary between at least two device cells of the plurality of device cells;
• depositing a second dielectric layer over the metal interconnect;
• and
• exposing at least one contact point on the metal interconnect through the second dielectric layer.