Skew management for PAM communication systems

A communication system comprising:

• a first communication lane comprising a first phase lock loop (PLL) and a first pattern generator, the first communication lane being configured to output a first data segment, the first pattern generator being configured to generate a first predetermined pattern, the first PLL being configured to generate a first clock signal;
• a second communication lane comprising a second PLL and a second pattern generator, the second PLL being configured to provide a second clock signal, the second PLL comprising a first sigma-delta modulator (SDM), the second communication lane being configured to output a second data segment, the second pattern generator being configured to generate a second predetermined pattern, the first SDM being configured to generate a first skew offset using a first analog offset signal for the second clock signal;
• a third communication lane comprising a third PLL and a third pattern generator, the third communication lane being configured to output a third data segment, the third pattern generator being configured to generate third predetermined pattern, the third PLL comprising a second SDM, the second SDM being configured to generate a second skew offset using a second analog offset signal for the third clock signal;
• a pulse amplitude modulation (PAM) circuit being configured to align the first data segment and the second data segment and the third data segment and output a PAM signal;
• a first skew management circuit being configured to generate the first analog offset signal, the first skew management circuit comprising a phase frequency detector (PFD) and a charge pump and a comparator, the PFD being configured to generate a control current by comparing the first predetermined pattern and the second predetermined pattern, the charge pump being configured to store the control current and characterized by a control voltage, the comparator being configured to generate the analog offset signal by comparing the control voltage to a predetermined reference voltage;
• and
• a second skew management circuit being configured to generate the second analog offset signal based at least on the second predetermined pattern and the third predetermined pattern.

A skew management device comprising:

• a first input selector circuit being configured to output a reference signal based on a first selected signal of two input signals, each of the two input signals comprising a predetermined pattern;
• a second selector circuit being configured to output a feedback signal based on a second selected signal of the two input signals;
• a phase frequency detector configured to generate a control current based on the reference signal and the feedback signal;
• an integrator circuit being configured to store the control current over a predetermined period of time and characterized by a control voltage;
• a comparator circuit being configured to generate an analog offset signal based on the control voltage and a reference voltage;
• and
• a reset circuit for discharging the integrator circuit.