Method and system for providing shared memory access to graphics processing unit processes
AssigneeNVIDIA Corporation
InventorNicholas Patrick Wilt
Life of this patent
Estimating the term…
Abstract
One or more embodiments of the invention set forth techniques to create a process in a graphical processing unit (GPU) that has access to memory buffers in the system memory of a computer system that are shared among a plurality of GPUs in the computer system. The GPU of the process is able to engage in Direct Memory Access (DMA) with any of the shared memory buffers thereby eliminating additional copying steps that have been needed to combine data output of the various GPUs without such shared access.
Claims22
A computer-implemented method for creating a first process that executes on a first graphics processing unit (GPU) within a plurality of GPUs included in a computer system, the method comprising:
- maintaining a list of a set of processes executing on the plurality of GPUs, wherein the set of processes includes the first process;
- maintaining a list of address range entries, wherein each address range entry in the list of address range entries comprises an address range corresponding to a different shared memory buffer in a set of shared memory buffers;
- requesting that an address space be allocated in the first GPU for the first process;
- requesting that the first GPU map the address range associated with each of the address range entries in the list of address range entries into the allocated address space, wherein a first address range is associated with a pinned memory buffer that is mapped into a second address space allocated in a second GPU within the plurality of GPUs;
- and
- adding the first process to the list of the set of processes, wherein the first process has access to any shared memory buffer corresponding to at least one of the address ranges mapped into the allocated address space.
A non-transitory computer-readable medium including instructions that, when executed by a processing unit, causes the processing unit to create a first process that executes on a first graphics processing unit (GPU) within a plurality of GPUs of a computer system, by performing the steps of:
- maintaining a list of a set of processes executing on the plurality of GPUs, wherein the set of processes includes the first process;
- maintaining a list of address range entries, wherein each address range entry in the list of address range entries comprises an address range corresponding to a different shared memory buffer in a set of shared memory buffers;
- requesting that an address space be allocated in the first GPU for the first process;
- requesting that the first GPU map the address range associated with each of the address range entries in the list of address range entries into the allocated address space, wherein a first address range is associated with a pinned memory buffer that is mapped into a second address space allocated in a second GPU within the plurality of GPUs;
- and
- adding the first process to the list of the set of processes, wherein the first process has access to any shared memory buffer corresponding to at least one of the address ranges mapped into the allocated address space.
A computing system configured to create a first process that executes on a first graphics processing unit (GPU), the computer system comprising:
- a system memory configured to store a set of shared memory buffers;
- the plurality of GPUs;
- and
- a processor coupled to the system memory, wherein the processor is configured perform the steps of:
- maintaining a list of a set of processes executing on the plurality of GPUs,
- maintaining a list of address range entries, wherein each address range entry in the list of address range entries comprises an address range corresponding to a different shared memory buffer in the set of shared memory buffers,
- requesting that an address space be allocated in the first GPU for the first process,
- requesting that the first GPU map the address range associated with each of the address range entries in the list of address range entries into the allocated address space, wherein a first address range is associated with a pinned memory buffer that is mapped into a second address space allocated in a second GPU within the plurality of GPUs, and
- adding the first process to the list of the set of processes, wherein the first process has access to any shared memory buffer corresponding to at least one of the address ranges mapped into the allocated address space.
Dependencies are inferred from the claim text.