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US 9,545,013 B2Granted
Flip chip interconnect solder mask
AssigneeSTATS ChipPAC Pte. Ltd.
InventorRajendra D. Pendse
Life of this patent
Estimating the term…
Abstract
A solder mask for flip chip interconnection has a common opening that spans a plurality of circuit elements. The solder mask allows confinement of the solder during the re-melt stage of interconnection, yet it is within common design rules for solder mask patterning. Also, a substrate for flip chip interconnection includes a substrate having the common opening that spans a plurality of circuit elements. Also, a flip chip package includes a substrate having a common opening that spans a plurality of circuit elements.
Claims19
A semiconductor device, comprising:
- a substrate;
- a masking layer including a plurality of elongated openings formed over a surface of the substrate;
- a plurality of traces formed over the surface of the substrate including a first portion of the plurality of traces passing beneath a first elongated opening of the plurality of elongated openings and parallel with respect to a first width across the first elongated opening and a second portion of the plurality of traces passing beneath a second elongated opening of the plurality of elongated openings and angled with respect to a second width across the second elongated opening;
- and
- a semiconductor die disposed over the substrate and including a plurality of contact pads electrically connected to interconnect sites on the traces.
2 more elements
A semiconductor device, comprising:
- a substrate;
- a masking layer formed over the surface of the substrate including a first elongated opening and a second elongated opening;
- a first trace and a second trace formed over the surface of the substrate including a first portion of the first and second traces passing beneath the first elongated opening and parallel with respect to a first width across the first elongated opening and a second portion of the first and second traces passing beneath the second elongated opening and angled with respect to a second width across the second elongated opening;
- a semiconductor die disposed over the substrate;
- and
- a plurality of bumps formed between contact pads of the semiconductor die and interconnect sites on the first and second traces within the first elongated opening, the bumps including a width at the surface of the substrate greater than a width of the interconnect sites.
3 more elements
A semiconductor device, comprising:
- a substrate;
- a masking layer including a first elongated opening and a second elongated opening formed over the surface of the substrate;
- and
- a first trace and a second trace formed over the surface of the substrate including a first portion of the first and second traces passing beneath the first elongated opening and parallel with respect to a first width across the first elongated opening and a second portion of the first and second traces passing beneath the second elongated opening and angled with respect to a second width across the second elongated opening.
1 more element
Dependencies are inferred from the claim text.