Reducing motion compensation memory bandwidth through memory utilization

A method for processing video information comprising:

• receiving encoded video information for a current video block of a current video frame;
• accessing, by decoder circuitry using n-bit access, encoded video processing information from the current video frame stored in a first memory;
• accessing, by the decoder circuitry using m-bit access, decoded reference video information from a previous video frame or decoded reference video information of one or more decoded video blocks of the current video frame that is stored in a second memory, wherein the second memory is dedicated to the decoder circuitry, wherein m is less than n;
• and
• utilizing, by the decoder circuitry, the encoded video processing information from the first memory and the decoded reference video information from the second memory to decode the received encoded video information for the current video block;
• and
• responsive to the received encoded video information for the current video block being decoded, storing decoded video information for the current video block to the second memory to update the decoded reference video information, and
• wherein the first memory resides on a first integrated circuit, and the second memory resides on a second integrated circuit, and
• wherein the second memory is utilized to store the decoded reference video information that is more efficiently accessed with narrower memory access, and the first memory is utilized to store the encoded video processing information that is more efficiently accessed with wider memory access.

A video processing system comprising:

• a first memory communicatively coupled to a decoder that stores non-reference video information from a current video frame and is accessible by the decoder using n-bit access;
• a second memory communicatively coupled to the decoder that stores reference video information from a previous video frame and is accessible by the decoder using m-bit access, wherein m is less than n;
• and
• wherein the decoder is configured to decode encoded video information of the current video frame utilizing the non-reference video information accessed from the first memory and the reference video information concurrently accessed from the second memory, wherein the second memory is dedicated to the decoder, and
• wherein, responsive to the encoded video information of the current video frame being decoded, the decoder stores decoded video information of the current video frame as updated reference video information to the second memory, and
• wherein the first memory resides on a first integrated circuit, and the second memory resides on a second integrated circuit, and
• wherein the second memory is utilized to store the reference video information that is more efficiently accessed with narrower memory access, and the first memory is utilized to store the non-reference video information that is more efficiently accessed with wider memory access.