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US 9,544,247 B2Granted
Packet data traffic management apparatus
AssigneeInnovasic, Inc.
InventorsAndrew David Alsup, Taylor M Wray, Kurt H Coonrod
Life of this patent
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Abstract
A packet data network traffic management device comprises a plurality of ports comprising at least a first port, a second port, and a third port; and a plurality of deterministic multi-threaded deterministic micro-controllers, each of the micro-controllers associated with a corresponding one of the ports to control packet data through the corresponding port; and the plurality of multi-threaded deterministic micro-controllers cooperatively operate to selectively communicate data packets between the plurality of ports.
Claims35
A packet data network traffic management device, comprising:
- a plurality of ports comprising at least a first port, a second port, and a third port;
- a plurality of deterministic multi-threaded micro-controllers, each of said deterministic multi-threaded microcontrollers associated with a corresponding one of said ports to control packet data through said corresponding port, each of said deterministic multi-threaded micro-controllers comprises a first hardware thread allocated to managing Incoming data packets on its said corresponding port and a second hardware thread allocated to managing outgoing data packets on said corresponding port, each of said first and second hardware threads are managed in hardware such that each thread executes an instruction on alternating clock cycles;
- a single memory, said single memory configured such that packet data from each of said plurality of ports may be routed therethrough;
- and
- said plurality of deterministic multi-threaded micro-controllers cooperatively operate to selectively communicate data packets between said plurality of ports.
2 more elements
A packet data network traffic management device, comprising:
- a first port;
- a second port;
- a third port;
- a first deterministic multi-threaded micro-controller controlling packet data traffic through said first port, said first deterministic multi-threaded micro-controller comprises a first hardware thread allocated to managing incoming data packets on said first port and a second hardware thread allocated to managing outgoing data packets on said first port, each of said first and second hardware threads are managed in hardware such that each of said first and second hardware thread executes an instruction on alternating clock cycles;
- a second deterministic multi-threaded micro-controller controlling packet data traffic through said second port said second deterministic multi-threaded micro-controller comprises a first hardware thread allocated to managing incoming data packets on said second port and a second hardware thread allocated to managing outgoing data packets on said second port, each of said first and second hardware threads are managed in hardware such that each of said first and second hardware thread executes an instruction on alternating clock cycles;
- a third deterministic multi-threaded micro-controller controlling packet data traffic through said third port, said third deterministic multi-threaded micro-controller comprises a first hardware thread allocated to managing incoming data packets on said third port and a second hardware thread allocated to managing outgoing data packets on said third port, each of said first and second hardware threads are managed in hardware such that each of said first and second hardware thread executes an instruction on alternating clock cycles;
- a single memory, said single memory configured such that packet data from each of said first, second and third ports may be routed therethrough;
- and
- said first deterministic multi-threaded micro-controller, said second deterministic multi-threaded micro-controller, and said third deterministic multi-threaded micro-controller cooperatively operate to selectively communicate packet data between each of said first, second and third ports.
6 more elements
Dependencies are inferred from the claim text.