Packet processing apparatus and packet processing method

A packet processing apparatus comprising:

• a processor configured to execute a process including:
• determining a memory from which first pointers are read, out of a second memory that stores the first pointers indicative of storage locations of packets in a first memory that stores the packets and a third memory that stores the first pointers, in accordance with a number of second pointers indicative of storage locations of the first pointers in the second memory;
• and
• reading the first pointers stored at the storage locations indicated by the second pointers, from the memory determined at the determining, wherein
• the determining includes, not actually reading the first pointers in a buffer which has not been read-accessed, but skipping read addresses of the first pointers by the number of the second pointers in another buffer which has actually been read.

A packet processing method comprising:

• determining a memory from which packets are read, out of a first memory that stores the packets and a second memory that stores the packets, in accordance with a number of pointers indicative of storage locations of the packets in the first memory by a processor;
• and
• reading the packets stored at the storage locations indicated by the pointers, from the determined memory by the processor, wherein
• the determining includes, not actually reading the pointers in a buffer which has not been read-accessed, but skipping read addresses of the pointers by the number of pointers in another buffer which has actually been read.