Multiphase receiver with equalization circuitry

An integrated circuit, comprising:

• a first circuit, including a first integrating receiver, to produce a first decision regarding a first logic state of a first data symbol associated with a first portion of a clock cycle;
• a second circuit, including a second integrating receiver, to produce a second decision regarding a second logic state of a second data symbol associated with a second portion of the clock cycle;
• and
• an equalizing circuit, having an input coupled to an output of the first integrating receiver of the first circuit and an output coupled to an output of the second integrating receiver of the second circuit, to compensate for intersymbol interference affecting the second circuit dependent on an output of the first circuit.

An integrated circuit, comprising:

• a first circuit, including a first receiver, to produce a first decision regarding a first logic state of a first data symbol associated with a first portion of a clock cycle;
• a second circuit, including a second receiver, to produce a second decision regarding a second logic state of a second data symbol associated with a second portion of the clock cycle;
• and
• an equalizing circuit, having an input coupled to an output of the first receiver of the first circuit and an output coupled to an output of the second receiver of the second circuit, to compensate for intersymbol interference affecting the second data symbol dependent on an output of the first circuit.