Method and apparatus for data aided timing recovery in 10GBASE-T system

A method of timing recovery performed by a first device, the method comprising:

• negotiating a pseudorandom number sequence with a second device;
• sampling a data signal received from the second device to recover a first training sequence;
• generating a second training sequence based on the pseudorandom number sequence;
• synchronizing the second training sequence with the first training sequence;
• and
• aligning a receive clock signal of the first device with the received data signal using the synchronized second training sequence, wherein aligning the receive clock signal comprises determining a timing error between the first training sequence and the synchronized second training sequence and adjusting the receive clock signal based on the timing error.

A non-transitory computer-readable storage medium configured to store program instructions that, when executed by a processor of a first device, cause the first device to:

• negotiate a pseudorandom number sequence with a second device;
• sample a data signal received from the second device to recover a first training sequence;
• generate a second training sequence based on the pseudorandom number sequence;
• synchronize the second training sequence with the first training sequence by comparing the first training sequence with the second training sequence;
• and iteratively adjusting the second training sequence based on the comparing, wherein comparing the first training sequence with the second training sequence comprises:
• determining a peak correlation between the first training sequence and the second training sequence by comparing each bit of the first training sequence with two or more bits of the second training sequence over a threshold number of data cycles, wherein the peak correlation is based on a number of matching bits within the first training sequence and the second training sequence and further based on a degree of variation between adjacent bits of the pseudorandom number sequence;
• and
• align a receive clock signal of the first device with the received data signal using the synchronized second training sequence.

A non-transitory computer-readable storage medium configured to store program instructions that, when executed by a processor of a first device, cause the first device to:

• negotiate a pseudorandom number sequence with a second device;
• sample a data signal received from the second device to recover a first training sequence;
• generate a second training sequence based on the pseudorandom number sequence;
• synchronize the second training sequence with the first training sequence;
• and
• align a receive clock signal of the first device with the received data signal using the synchronized second training sequence, wherein aligning the receive clock signal comprises determining a timing error between the first training sequence and the synchronized second training sequence, and adjusting the receive clock signal based on the timing error.

A device, comprising:

• a processor to negotiate a pseudorandom number sequence with another device;
• an analog-to-digital converter (ADC) to sample a data signal received from the other device to recover a first training sequence;
• a training sequence generator to generate a second training sequence based on the pseudorandom number sequence;
• a data synchronization circuit to synchronize the second training sequence with the first training sequence;
• and
• a timing alignment circuit to align a receive clock signal of the device with the received data signal using the synchronized second training sequence;
• wherein the data synchronization circuit comprises:
• a peak detection circuit to compare the first training sequence with the second training sequence, the peak detection circuit comprising a plurality of comparators to compare each bit of the first training sequence with two or more bits of the second training sequence to generate a plurality of match values and a peak detect logic to determine a peak correlation between the first training sequence and the second training sequence based on the plurality of match values;
• and
• a data adjustment circuit to iteratively adjust the second training sequence based on the comparison.