Switching architecture with packet encapsulation

A process for passing Time Division Multiplexing (TDM) traffic through a packet switch having a plurality of data ports and being capable of routing Fixed Size Data Unit (FSDU) packets between the plurality of data ports, the process comprising;

• encapsulating a TDM data flow by sorting the TDM data flow into different respective buffer locations;
• generating an FSDU that can pass through the packet switch and filling the generated FSDU with data associated with a respective one of the TDM circuits;
• generating header information representative of information for routing the generated FSDU to a port associated with the respective one of the TDM circuits;
• combining the generated FSDU with a flow of packet data being sent to the packet switch;
• and
• with a jitter buffer, reducing variable delays arising from passing through the packet switch, wherein the jitter buffer has a size selected to maintain jitter below 125 microseconds.

A process for passing Time Division Multiplexing (TDM) traffic through a packet switch having a plurality of data ports and being capable of routing Fixed Size Data Unit (FSDU) packets between the plurality of data ports, the process comprising;

• encapsulating a TDM data flow by sorting the TDM data flow into different respective buffer locations;
• generating an FSDU that can pass through the packet switch and filling the generated FSDU with data associated with a respective one of the TDM circuits;
• generating header information representative of information for routing the generated FSDU to a port associated with the respective one of the TDM circuits;
• combining the generated FSDU with a flow of packet data being sent to the packet switch;
• and
• setting a timer to establish a time period for filling the generated FSDU, wherein the time period is set to a TDM frame boundary period.