US 9,544,078 B2Granted

Method and system for optimizing short term stability of a clock pulse

AssigneeRohde & Schwarz GmbH & Co. KG

InventorNorman Herzog

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Abstract

A system for optimizing short-term stability of a clock source clock pulse synchronized with a long-term stable reference-clock transmits clock numbers of a first reference clock to the clock source, between an initialization time and several times within a data-packet network. The clock pulse is adjusted by controlling a difference between clock numbers of the first reference clock received in the clock source and clock numbers of the first reference clock between the initialization time and the reception times of the clock numbers of the first reference clock. Clock numbers of a second reference clock are transmitted to the clock source with the clock number of at least one second reference-clock source at individual times. The maximum difference between the first and the second reference clock is known. The difference between the clock pulse of the clock source and each second reference clock is limited to an adjustable threshold value.

Claims15

Dependent claims

A method comprising:

transmitting clock-cycle numbers of a first reference clock signal of a first reference-clock source to a clock source between an initialization time and several times within a data-packet network, wherein the clock source is synchronized with a first long-term stable reference-clock source;
adjusting a clock pulse of the clock source by controlling a difference between clock-cycle numbers of the first reference clock signal received in the clock source and clock-cycle numbers of the first reference clock signal between the initialization time and the respective reception times of the clock-cycle numbers of the first reference clock signal, wherein the frequency of a frequency oscillator integrated in a phase control is used for matching the received clock-cycle numbers of the first reference clock signal;
transmitting clock-cycle numbers of at least one second reference clock signal of a data packet, which receives the clock-cycle number from at least one second, free-running reference-clock source at individual times to the clock source;
and
limiting the difference between the clock pulse of the clock source and each second reference clock signal to a first adjustable threshold value.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/367,934Filed 20 Dec 2012
Priority: DE 10 2011 089 72123 Dec 2011
Published: US 2015/0016476 A115 Jan 2015
Granted: 10 Jan 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H04J 3/0697
Clock or time synchronisation in a node; Intranode synchronisation: synchronisation in a packet node
H04J 3/0635
Synchronising arrangements: clock or time synchronisation in a network
H04J 3/0658
Clock or time synchronisation among nodes; Internode synchronisation: clock or time synchronisation among packet nodes
H04N 21/242
Processing of content or additional data; Elementary server operations; Server middleware: synchronisation processes, e.g. processing of PCR…