Efficient storage architecture for low-density parity-check decoding

A low-density parity-check (LDPC) decoder comprising, a set of shift registers configured to:

• receive LDPC coded data;
• decode the LDPC coded data to create output data,
• each shift register, of the set of shift registers, performing at least one iteration associated with decoding the LDPC coded data;
• and
• provide the output data;
• where each shift register, of the set of the shift registers, includes:
• a quantity of lanes corresponding to a quantity of data words received by the shift register at a particular clock cycle;
• a quantity of stages corresponding to a quantity of clock cycles needed to perform an iteration associated with decoding the LDPC coded data;
• a quantity of storage elements, associated with storing the data words during the iteration, and a set of check node functions associated with updating data words during the iteration;
• a value of the quantity of storage elements being less than a value of the quantity of stages times a value of the quantity of lanes by a value representing a particular number of storage elements,
• the particular number of storage elements being displaced by the set of check node functions.

An optical receiver, including a low-density parity-check (LDPC) decoder, comprising:

• a shift register configured to:
• receive LDPC coded data;
• perform an iteration associated with decoding the LDPC coded data;
• and
• provide a result associated with performing the iteration associated with decoding the LDPC coded data;
• where the shift register includes:
• a quantity of shift register lanes corresponding to a quantity of data words received by the shift register at a particular time,
• a quantity of shift register stages corresponding to a quantity of clock cycles associated with performing the iteration associated with decoding the LDPC coded data, and
• a quantity of storage elements, associated with storing the data words during the iteration, and a group of check node elements associated with updating the data words during the iteration,
• a value representing the quantity of shift register stages times a value representing the quantity of shift register lanes being greater than a value representing the quantity of storage elements by a value representing a particular number of storage elements,
• the particular number of storage elements being displaced by the group of check node elements.