Decoding method, memory storage device and memory control circuit unit

A memory storage device, comprising:

• a connection interface unit, configured to be coupled to a host system;
• a rewritable non-volatile memory module, comprising a plurality of memory cells;
• and
• a memory control circuit unit, coupled with the connection interface unit and the rewritable non-volatile memory module,
• wherein the memory control circuit unit is configured to send a read command sequence for reading the plurality of memory cells so as to obtain a plurality of first bits,
• the memory control circuit unit is further configured to determine whether the first bits have at least one first error,
• if the first bits have the at least one first error, the memory control circuit unit is further configured to execute a first iteration decoding procedure on the first bits so as to obtain a plurality of second bits, and record first bit flipping information of the first iteration decoding procedure,
• the memory control circuit unit is further configured to determine whether the second bits have at least one second error,
• if the second bits have the at least one second error, the memory control circuit unit is further configured to execute a second iteration decoding procedure on the second bits according to the first bit flipping information so as to obtain a plurality of third bits,
• if the second bits do not have the at least one second error, the memory control circuit unit is further configured to output the second bits,
• the memory control circuit unit is further configured to record second bit flipping information of the second iteration decoding procedure according to the first bit flipping information,
• the memory control circuit unit is further configured to determine whether the third bits have at least one third error,
• if the third bits have the at least one third error, the memory control circuit unit is further configured to execute a third iteration decoding procedure on the third bits according to the second bit flipping information so as to obtain a plurality of fourth bits, and
• if the third bits do not have the at least one third error, the memory control circuit unit is further configured to output the third bits,
• wherein the second bit flipping information indicates a specific bit among the third bits having a bit value different from an original bit value of said specific bit among the first bits.

A memory control circuit unit, configured to control a rewritable non-volatile memory module comprising a plurality of memory cells, the memory control circuit unit comprising:

• a host interface, configured to be coupled to a host system;
• a memory interface, configured to be coupled to the rewritable non-volatile memory module;
• a memory management circuit, coupled with the host interface and the memory interface and configured to send a read command sequence for reading the plurality of memory cells so as to obtain a plurality of first bits;
• and
• an error checking and correcting circuit, coupled to the memory management circuit and configured to determine whether the first bits have at least one first error, wherein
• if the first bits have the at least one first error, the error checking and correcting circuit is further configured to execute a first iteration decoding procedure on the first bits so as to obtain a plurality of second bits and record first bit flipping information of the first iteration decoding procedure,
• the error checking and correcting circuit is further configured to determine whether the second bits have at least one second error,
• if the second bits have the at least one second error, the error checking and correcting circuit is further configured to execute a second iteration decoding procedure on the second bits according to the first bit flipping information so as to obtain a plurality of third bits,
• if the second bits do not have the at least one second error, the error checking and correcting circuit is further configured to output the second bits,
• the error checking and correcting circuit is further configured to record second bit flipping information of the second iteration decoding procedure according to the first bit flipping information,
• the error checking and correcting circuit is further configured to determine whether the third bits have at least one third error,
• if the third bits have the at least one third error, the error checking and correcting circuit is further configured to execute a third iteration decoding procedure on the third bits according to the second bit flipping information so as to obtain a plurality of fourth bits, and
• if the third bits do not have the at least one third error, the error checking and correcting circuit is further configured to output the third bits,
• wherein the second bit flipping information indicates a specific bit among the third bits having a bit value different from an original bit value of said specific bit among the first bits.