Circuit for digitizing phase differences, PLL circuit and method for the same

A method, comprising:

• detecting a phase difference between a DCO output signal and a reference clock signal, and generating a difference signal based on the detected phase difference;
• generating a control code based upon the difference signal;
• and
• generating the DCO output signal responsive to the control code,
• wherein the control code causes the DCO output signal to be adjusted to reduce the phase difference between the DCO output signal and the reference clock signal;
• wherein generating the control code based upon the difference signal comprises propagating a starting edge of a first pulse of the difference signal through a latch chain until the latch chain is disabled in response to an ending edge of the first pulse.

A circuit, comprising:

• a detecting circuit configured to detect a phase difference between a first clock signal and a second clock signal, and generate a difference signal based on the detected phase difference;
• and
• a digitized difference generator, coupled to the detecting circuit, configured to generate a control code based upon the difference signal;
• wherein the difference signal comprises a signal UP and a signal DN, when the first clock signal lags the second clock signal, the signal UP is used to reflect the phase difference, and when the first clock signal leads the second clock signal, the signal DN is used to reflect the phase difference;
• wherein the digitized difference generator comprises an UP latch chain and a DN latch chain, the UP latch chain propagates a starting edge of a first pulse of the signal UP until the UP latch chain is disabled in response to an ending edge of the first pulse, the DN latch chain propagates a starting edge of a second pulse of the signal DN until the DN latch chain is disabled in response to an ending edge of the second pulse, and outputs of latches of the UP latch chain and outputs of latches of the DN latch chain form the control code.