Interposer with embedded clock network circuitry
AssigneeAltera Corporation
InventorWeiqi Ding
Life of this patent
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Abstract
An integrated circuit package includes an interposer with an embedded clock network formed by multiple clock trees. A die with first and second clock circuits is disposed over the interposer. At least one of the first and second clock trees is a resonant clock tree and both the first and second clock circuits may provide clock signals at different frequencies. The first clock circuit may provide clock signals at one frequency to a clock tree in the embedded clock network while the second clock circuit may provide clock signals at another frequency to another clock tree in the embedded clock tree network.
Claims20
An integrated circuit package comprising:
- an interposer with a plurality of clock trees forming an embedded clock network;
- and
- a die having first and second clock circuits disposed over the interposer, wherein the first clock circuit provides clock signals at a first frequency to a first clock tree of the plurality of clock trees, wherein the second clock circuit provides clock signals at a second frequency that is different from the first frequency to a second clock tree of the plurality of clock trees, and wherein at least one of the first and second clock trees comprises a resonant clock tree.
An integrated circuit package comprising:
- a die having a plurality of clock sources;
- and
- an interposer coupled to the die via a plurality of interconnects, wherein the interposer comprises a resonant clock tree network that is driven by a clock signal generated by at least one clock source of the plurality of clock sources on the die, and wherein a given one of the plurality of interconnects transmits the clock signal from the resonant clock tree network on the interposer to the die.
A method of forming a clock network for an integrated circuit in an integrated circuit package, the method comprising:
- forming a plurality of resonant clock trees in an interposer;
- selectively routing clock signals from a first clock source on the integrated circuit to a first resonant clock tree of the plurality of clock trees;
- selectively routing clock signals from a second clock source on the integrated circuit to a second resonant clock tree of the plurality of clock trees;
- and
- selectively routing clock signals from the first and second resonant clock trees via through silicon vias in the interposer to the integrated circuit, wherein the first and second resonant clock trees form at least a portion of the clock network for the integrated circuit.
Dependencies are inferred from the claim text.