Multi-stage frequency dividers having duty cycle correction circuits therein

A multi-stage frequency divider, comprising:

• a divider circuit responsive to a periodic reference signal to be divided, said divider circuit having at least first and second integer dividers therein, which are electrically coupled in a cascaded arrangement so that the second integer divider receives, at an input thereof, an intermediate divider signal derived from a first output of the first integer divider;
• a duty cycle enhancement circuit configured to generate an intermediate output signal having an N/N+1 duty cycle in response to at least first and second output signals generated by said divider circuit, where:
• (i) N is a positive integer and 2N+1 equals a product of a first divide value of the first integer divider and a second divide value of the second integer divider, and (ii) at least one of the first and second output signals has a duty cycle less than the N/N+1 duty cycle;
• and
• a duty cycle correction circuit configured to generate a periodic output signal having a uniform duty cycle and a period equal to the product times a period of the periodic reference signal, in response to the intermediate output signal having the N/N+1 duty cycle.