Phase-mode based superconducting logic

A method in a device comprising:

• (1) a plurality of Josephson junctions, (2) at least one latch, and (3) a plurality of logic gates comprising at least a subset of the plurality of Josephson junctions, the method comprising:
• receiving a return-to-zero clock signal;
• receiving an input signal;
• using the plurality of logic gates, processing the input signal and the return-to-zero clock signal to generate a first signal for the at least one latch;
• using at least a phase-mode logic inverter, processing the return-to-zero clock signal to generate a second signal for the at least one latch;
• and
• based on at least the first signal and the second signal, providing an output of the at least one latch.

A device comprising:

• a plurality of Josephson junctions;
• at least one terminal for receiving an input signal;
• at least one clock terminal for receiving a return-to-zero clock signal;
• at least one latch;
• at least one logic gate, comprising at least a subset of the plurality of Josephson junctions, for processing the input signal and the return-to-zero clock signal to generate a first signal for the at least one latch;
• at least one inverter for processing the return-to-zero clock signal to generate a second signal for the at least one latch;
• and
• at least one output terminal for providing an output of the at least one latch by processing the first signal and the second signal, wherein the output of the at least one latch is persistent across at least four phases of a sinusoidal clock signal.