Multiplexer-memory cell circuit, layout thereof and method of manufacturing same

An integrated circuit disposed in and on a substrate, the integrated circuit comprising:

• a plurality of logic tiles, wherein each logic tile includes a plurality of edges and, is configurable to communicate, during operation, with at least one logic tile that is adjacent to an edge, and wherein a first logic tile of the plurality of logic tiles includes:
• a plurality of memory cells to store data, wherein each memory cell includes a first output;
• a first multiplexer including a plurality of inputs, an output and a plurality of input selects;
• a first plurality of poly-silicon conductors, each poly-silicon conductor of the first plurality is disposed in the substrate and connected to the first output of an associated memory cell;
• a first plurality of poly-silicon extensions, each poly-silicon extension having a first end and a second end, wherein each poly-silicon extension of the first plurality is (i) connected at a first end to an associated poly-silicon conductor of the first plurality of poly-silicon conductors and (ii) coupled at a second end to an associated input select of the first multiplexer, wherein the first plurality of poly-silicon extensions are disposed in the substrate and at least partially under a first metal conductor in the first logic tile;
• a second multiplexer including a plurality of inputs, an output and a plurality of input selects;
• and
• a second plurality of poly-silicon extensions, each poly-silicon extension of the second plurality having a first end and a second end, wherein each poly-silicon extension of the second plurality is (i) coupled at a first end to a second end of a unique poly-silicon extension of the first plurality of poly-silicon extensions and (ii) coupled at a second end to an associated input select of the second multiplexer, wherein the second plurality of poly-silicon extensions are disposed in the substrate and at least partially under a second metal conductor in the first logic tile.

An integrated circuit disposed in and on a substrate, the integrated circuit comprising:

• a plurality of logic tiles, wherein each logic tile includes a plurality of edges and, is configurable to communicate, during operation, with at least one logic tile that is adjacent to an edge, and wherein a first logic tile of the plurality of logic tiles includes:
• a plurality of static memory cells to store data, wherein each memory cell includes a first output;
• a multiplexer including a plurality of inputs, an output and a plurality of input selects;
• a first plurality of poly-silicon conductors, each poly-silicon conductor is disposed in the substrate and connected to the first output of an associated memory cell;
• poly-silicon extensions, each poly-silicon extension is (i) connected to an associated poly-silicon conductor of the first plurality of poly-silicon conductors and (ii) coupled to an associated input select of the multiplexer, wherein the poly-silicon extensions are disposed in the substrate and at least partially under a metal conductor in the first logic tile;
• and
• a second plurality of poly-silicon conductors, each poly-silicon conductor of the second plurality includes first and second ends and is disposed in the substrate, wherein the first end is connected to the associated poly-silicon extension and the second end is connected at the associated input select of the multiplexer.