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US 9,543,956 B2Granted
Systems and methods for configuring an SOPC without a need to use an external memory
AssigneeIntel Corporation
InventorsWoi Jie Hooi, Kok Heng Choe
Life of this patent
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Abstract
Systems and techniques for configuration of a system on a programmable chip (SOPC) are described. By configuring the SOPC, during power-up, with a voltage input instead of with a flash memory or another non-volatile memory, the systems and techniques may save cost and board space.
Claims14
A system comprising:
- a first voltage input;
- a second voltage input;
- a system on a programmable chip (SOPC) including a core and an interface;
- a plurality of configuration shift registers;
- and
- a multiplexer configured to multiplex between an output of the first voltage input or an output of at least one of the plurality of configuration shift registers based on a value of a user-mode bit, wherein:
- the interface is configured to communicate with a host via a link;
- during a first mode, the SOPC receives a first set of configuration data from the host via the interface and the SOPC configures, via the first voltage input and the second voltage input, the plurality of configuration shift registers to store the first set of configuration data;
- during a second mode, the SOPC receives a second set of configuration data from the host via the interface and the SOPC configures, via the first voltage input and the second voltage input, the plurality of configuration shift registers to store the second set of configuration data;
- during at least one of the first mode and the second mode, use of non-volatile memory is restricted;
- during the second mode, a first configuration of the core is established via the first or second voltage input;
- and
- during a third mode, the interface is configured by the second set of configuration data stored in the plurality of configuration shift registers in response to the first configuration of the core and the configuration of the plurality of the configuration shift registers.
10 more elements
A method comprising:
- receiving, during a first mode, at a system on a programmable chip (SOPC), a first set of configuration data from a host;
- storing a plurality of configuration bits in a plurality of configuration shift registers of the SOPC, wherein said storing the plurality of configuration bits is performed by configuring, via a first voltage input and a second voltage input, the plurality of configuration shift registers of the SOPC based on the configuration data received from the host, wherein during the first mode use of non-volatile memory is restricted;
- multiplexing between an output of the first voltage input or an output of a configuration shift register based on a value of a user-mode bit;
- and
- configuring, during a second mode, a core of the SOPC, wherein said configuring the core and the plurality of configuration shift registers is performed in response to the first set of configuration data.
2 more elements
A system comprising:
- a host;
- a system on a programmable chip (SOPC) including a core and an interface, wherein the interface is coupled to the host via a link;
- a first voltage source;
- a second voltage source, and
- a plurality of configuration shift registers, and
- a multiplexer configured to multiplex between an output of the first voltage input or an output of at least one of the plurality of configuration shift registers based on a value of a user-mode bit, wherein
- during a first mode, the interface is configured by applying voltage from the first voltage source or the second voltage source;
- and
- during a second mode, the SOPC receives a second set of configuration data from the host via the interface and the SOPC configures, via the first voltage input and the second voltage input, the plurality of configuration shift registers to store the second set of configuration data;
- during at least one of the first mode and the second mode, use of non-volatile memory is restricted;
- during the second mode, a first configuration of the core is established via the first or second voltage input;
- and
- during a third mode, the interface is configured by the second set of configuration data stored in the plurality of configuration shift registers in response to the first configuration of the core and the configuration of the plurality of the configuration shift registers.
10 more elements
Dependencies are inferred from the claim text.