US 9,543,953 B2Granted

Semiconductor device having floating body type transistor

AssigneeLongitude Semiconductor S.a.r.l.

InventorSoichiro Yoshida

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Abstract

A semiconductor device includes a first circuit node supplied with a first signal changing between first and second logic levels, a second circuit node supplied with a second signal changing between the first and second logic levels, a third circuit node, a first transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the second and third circuit nodes, the first transistor being rendered conductive when the first signal is at the second logic level, a fourth circuit node supplied with a voltage level being close to or the same as the second logic level, and a second transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the third and fourth circuit nodes, the second transistor being rendered conductive when the first signal is at the first logic level.

Claims17

Dependent claims

A semiconductor device comprising:

a first circuit node supplied with a first signal changing between first and second logic levels;
a second circuit node supplied with a second signal changing between the first and second logic levels;
a third circuit node;
a first transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the second and third circuit nodes, the first transistor being rendered conductive when the first signal is at the second logic level;
a fourth circuit node supplied with a voltage level being close to or the same as the second logic level;
and
a second transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the third and fourth circuit nodes, the second transistor being rendered conductive when the first signal is at the first logic level, the first transistor being configured as a floating body type in which a body between a source and a drain is in an electrically floating state;
a fifth circuit node supplied with a third signal changing between the first and second logic levels;
a third transistor having a gate electrically connected to the fifth circuit node and a source-drain path electrically connected in series with the first transistor between the second and third circuit nodes, the third transistor rendered conductive when the third signal is at the second logic level;
and
a fourth transistor having a gate electrically connected to the fifth circuit node and a source-drain path electrically connected in parallel with the second transistor between the third and fourth circuit nodes, the third transistor rendered conductive when the third signal is at the first logic level, the third transistor being configured as the floating body type.

8 more elements

A semiconductor device comprising first and second logic circuits, each of the first and second logic circuits comprising:

a first transistor including first and second electrodes, a gate electrode, and a body electrode between the first and second electrodes thereof, the first transistor being of a first conductivity type;
a second transistor including first and second electrodes, a gate electrode, and a body electrode between the first and second electrodes thereof, the second transistor being of a second conductivity type different from the first conductivity type;
a third transistor including first and second electrodes, a gate electrode, and a body electrode between the first and second electrodes thereof, the third transistor being of the first conductivity type, and the third transistor being coupled in series with the first transistor;
a fourth transistor including first and second electrodes, a gate electrode, and a body electrode between the first and second electrodes thereof, the fourth transistor being of the second conductivity type, and the fourth transistor being coupled in parallel with the second transistor;
a first circuit node coupled to each of the gate electrode of the first transistor and the gate electrode of the second transistor, and being supplied with a first signal changing between the first and second logic levels;
a second circuit node coupled to the first electrode of the first transistor, and being supplied with a second signal changing between first and second logic levels;
a third circuit node coupled to each of the second electrode of the third transistor, the second electrode of the second transistor, and the second electrode of the fourth transistor;
a fourth circuit node coupled to each of the first electrode of the second transistor and the first electrode of the fourth transistor, and being supplied with the second level;
and
a fifth circuit node coupled to each of the gate electrode of the third transistor and the gate electrode of the fourth transistor, and being supplied with a third signal changing between the first and second logic levels;
each of the first and third transistors being configured as a floating body type in which a body electrode is in an electrically floating state.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/967,267Filed 14 Aug 2013 · division
Priority: JP 2010-09356514 Apr 2010
Published: US 2013/0328590 A112 Dec 2013
Granted: 10 Jan 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H03K 19/018507
Using field effect transistors only: interface arrangements
G11C 7/1048
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data bus control circuits, e.g. precharging,…
G11C 11/4091
Read-write [R-W] circuits: sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or…
G11C 11/4096
Read-write [R-W] circuits: input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches

Family

Application13/064,716Parent of this division · filed 11 Apr 2011
US 2013/0328590 A1Pre-grant publication · published 12 Dec 2013
US 8,537,635 B2Parent of this division
US 2011/0255358 A1Published application
US 9,543,953 B2This patent

From the US filing history. Foreign family members aren’t listed.