Multi-phase clock generation
AssigneeMicrosoft Technology Licensing, LLC
InventorAlan S. Fiedler
Life of this patent
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Abstract
Embodiments are disclosed that relate to multi-phase clock generators and data samplers for use in high speed I/O circuitry. One disclosed example provides a multi-phase clock generator including a delay line having a plurality of delay elements, the delay line being configured to receive an input clock signal and output a plurality of output clock signals having different phases compared to a phase of the input clock signal. The multi-phase clock generator further includes a control circuit configured to control the delay line based at least in part upon rising edges and falling edges of one or more output clock signals output at one or more locations along the delay line.
Claims20
A device, comprising:
- a first delay line having a plurality of delay elements, the first delay line being configured to receive a first input clock signal and output a first plurality of output clock signals having different phases compared to a phase of the first input clock signal;
- a second delay line having a plurality of delay elements, the second delay line being configured to receive a second input clock signal and output a second plurality of output clock signals having different phases compared to a phase of the second input clock signal;
- a control circuit configured to control the first and second delay lines based at least in part upon a rising or falling edge of at least one output clock signal of the first plurality of output clocks signals and at least one output clock signal of the second plurality of output clock signals;
- and
- a crossover control module communicatively coupled to the delay line, the crossover control module being configured to receive clock signals from a clock signal source, determine crossover error in the first and second delay lines, and generate the first input clock signal and the second input clock signal based on the crossover error.
A device, comprising:
- a first delay line having a first plurality of delay elements;
- a second delay line having a second plurality of delay elements, the first delay line and the second delay line being in electrically parallel paths and forming pairs of delay elements;
- and
- a module electrically coupled to the first delay line and the second delay line and configured to:
- receive complementary clock input signals from a clock signal source,
- receive a first pair of output signals from a first pair of delay elements,
- utilize a signal crossover point of the first pair of output signals to adjust a crossover point in the complementary clock input signals to form adjusted complementary clock input signals, and
- output the adjusted complementary clock input signals to the first and second delay lines.
A multi-phase clock generator, comprising:
- electrically parallel first and second delay lines having a plurality of complementary delay elements;
- an input buffer and crossover control module configured to receive a first source clock input signal and a second source clock input signal from a clock signal source, the second source clock input signal being complementary to the first source clock input signal, the input buffer and crossover control module further configured to receive feedback signals from the electrically parallel first and second delay lines, and to output to the electrically parallel first and second delay lines complementary clock input signals by determining crossover error in the first source clock input signal and the second source clock input signal based at least in part upon the feedback signals received from the electrically parallel first and second delay lines;
- and
- a control circuit configured to control the electrically parallel first and second delay lines based at least in part upon rising and falling edges of one or more output clock signals output at one or more locations along the electrically parallel first and second delay lines.
Dependencies are inferred from the claim text.