Determination of configuration values and configuration of frequency multiplier and frequency divider circuitry

A method of configuring a programmable integrated circuit (IC), comprising:

• inputting respective requested frequency values and respective tolerance levels relative to the requested frequency values for a plurality of clocked circuit blocks, each clocked circuit block having a respective clock input port;
• determining by a computer processor, a plurality of solution sets, each solution set including a multiplier value and an associated set of values of divisors, wherein:
• respective subsets of each set of values of divisors correspond to the clocked circuit blocks, and each subset includes one or more values of one or more corresponding divisors, and
• for each solution set, for each clocked circuit block an actual frequency value that is a function of an oscillator frequency, the multiplier value, and the respective subset of the one or more values of the one or more corresponding divisors, satisfies the respective tolerance level;
• determining respective sets of clocked error values for the plurality of solution sets, each set of clocked error values including for each clocked circuit block a respective clocked error value that is a function of the respective requested frequency value of the clocked circuit block, the oscillator frequency, the multiplier value, and the value of the divisor corresponding to the clocked circuit block;
• determining for each solution set a respective solution-set-error value as a function of the respective clocked error values;
• selecting one of the solution sets having a respective solution-set-error value that is less than the respective solution-set-error value of each other of the solution sets;
• and
• configuring a frequency multiplier circuit and frequency divider circuits coupled between an oscillator of the programmable IC and the clocked circuit blocks with the multiplier value and values of the divisors from the one solution set for providing clock signals to the clock input ports of the clocked circuit blocks.

A system, comprising:

• a processor;
• a memory arrangement coupled to the processor, wherein the memory arrangement is configured with instructions that are executable by the processor for performing operations including:
• inputting respective requested frequency values and respective tolerance levels relative to the requested frequency values for a plurality of clocked circuit blocks, each clocked circuit block having a respective clock input port;
• determining a plurality of solution sets, each solution set including a multiplier value and an associated set of values of divisors, wherein:
• each value of a divisor in each associated set corresponds to one of the clocked circuit blocks,
• an actual frequency value for the corresponding clocked circuit block is a function of an oscillator frequency, the multiplier value, and the value of the divisor, and
• the actual frequency value satisfies the respective tolerance level;
• determining respective sets of clocked error values for the plurality of solution sets, each set of clocked error values including for each clocked circuit block a respective clocked error value that is a function of the respective requested frequency value of the clocked circuit block, the oscillator frequency, the multiplier value, and the value of the divisor corresponding to the clocked circuit block;
• determining for each solution set, a respective solution-set-error value as a function of the respective sets of clocked error values;
• selecting one of the solution sets having a respective solution-set-error value that is less than the respective solution-set-error value of each other of the solution sets;
• and
• storing the one solution set in the memory arrangement.