Low-voltage to high-voltage level shifter circuit

A low-voltage to high-voltage level shifter circuit, comprising:

• an input circuit configured to receive an input signal having a voltage range between a first voltage and a ground voltage, and to provide an inverted input signal and a delayed version of the inverted input signal, the input circuit including a plurality of MOS transistors, each of the plurality of MOS transistors with a gate oxide of a first thickness;
• a voltage shifting circuit coupled to the input circuit and configured to receive the input signal, the inverted input signal, and the delayed version of the inverted input signal and to provide an internal signal having a voltage range between a second voltage and the ground voltage, the second voltage being higher than the first voltage, the voltage shifting circuit including a first plurality of MOS transistors, each of the first plurality of MOS transistors with a gate oxide of the first thickness, and a second plurality of MOS transistors, each of the second plurality of MOS transistors with a gate oxide of a second thickness greater than the first thickness;
• an output circuit coupled to the voltage shifting circuit and configured for receiving the internal signal and to provide an output signal having a voltage range between the second voltage and the ground, the output circuit including a plurality of MOS transistors, each with a gate oxide of the second thickness;
• wherein:
• if the input signal is at the first voltage, the output signal is at the second voltage, and
• if the input signal is at the ground voltage, the output signal is at the ground voltage.

A low-voltage to high-voltage level shifter circuit, comprising:

• an input circuit configured to receive an input signal having a voltage range between a first voltage and a ground voltage, and to provide an inverted input signal and a delayed version of the inverted input signal, the input circuit comprising a first MOS transistor and a second MOS transistor;
• a voltage shifting circuit coupled to the input circuit and configured to receive the input signal, the inverted input signal, and the delayed version of the input signal and to provide an internal signal having a voltage range between a second voltage and the ground voltage, the second voltage being higher than the first voltage, the voltage shifting circuit comprising third, fourth, fifth, sixth, seventh, eighth, and ninth MOS transistors;
• and
• an output circuit coupled to the voltage shifting circuit and configured to receive the internal signal and to provide an output signal having a voltage range between the second voltage and the ground voltage,
• wherein the third, fifth, sixth and eighth MOS transistors are coupled in series between the ground voltage and the second voltage,
• wherein the fourth, seventh, and ninth MOS transistors are coupled in series between the ground voltage and the second voltage.