Differential amplifier circuit and semiconductor memory device including same
AssigneeSK hynix Inc.
InventorsHan Qu, Kyoung-Han Kwon
Life of this patent
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Abstract
Disclosed are a differential amplifier circuit and a semiconductor memory device including the same, wherein the differential amplification circuit includes: a differential amplifier activated in response to an enable signal, capable of differentially amplifying input signals inputted through input terminals and outputting output signals; and an operation control section capable of sequentially applying signals having a voltage difference increasing in stepped fashion to the input terminals of the differential amplifier, measuring voltages of the output signals of the differential amplifier to detect an input offset, and adjusting an activation timing of the enable signal depending on a detected offset.
Claims20
A differential amplification circuit comprising:
- a differential amplifier activated in response to an enable signal, capable of differentially amplifying input signals inputted through input terminals and outputting output signals;
- and
- an operation control section capable of sequentially applying signals having a voltage difference increasing in stepped fashion to the input terminals of the differential amplifier, measuring voltages of the output signals of the differential amplifier to detect an input offset, and adjusting an activation timing of the enable signal depending on a detected offset.
A differential amplification circuit comprising:
- a differential amplifier activated in response to an enable signal, capable of differentially amplifying input signals inputted through input terminals and outputting output signals;
- an offset controller capable of generating a test enable signal activated in an assigned period, generating step voltages having a voltage difference increasing in stepped fashion when the test enable signal is activated, providing the test enable signal and the step voltages as the inputs signals and an enable signal of the differential amplifier, and measuring voltages of the output signals of the differential amplifier to detect an input offset, during a test mode;
- and
- a timing control unit capable of adjusting an activation timing of the enable signal depending on a detected offset during a normal mode.
A semiconductor memory device comprising:
- a sense amplifier circuit which comprises N number of sense amplifiers which are capable of being activated in response to an enable signal, and sensing and amplifying external input data of a plurality of local line pairs to output output data to a plurality of global line pairs;
- and
- an operation control section capable of sequentially applying, during a test mode, signals having a voltage difference increasing in stepped fashion to input terminals of each sense amplifier, measuring voltages of the output data of the sense amplifiers to detect an input offset, and adjusting an activation timing of the enable signal depending on a detected offset.
Dependencies are inferred from the claim text.