MOSFET driver with pulse timing pattern fault detection and adaptive safe operating area mode of operation
AssigneePower Integrations, Inc.
InventorsArthur B. Odell, Leif Lund, Sujit Banerjee
Life of this patent
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Abstract
A Safe Operating Area (SOA) adaptive gate driver for a switch mode power converter is disclosed. In response to a detection of a fault condition, the SOA adaptive gate driver may limit the peak current in a power transistor (e.g., power MOSFET) of the power converter by limiting the voltage applied to the gate of the power MOSFET or by limiting the current injected into the gate of the power MOSFET. The limited gate voltage or current may increase the margin between an SOA border and the turn-off locus of the drain voltage and current (VD and ID) to ensure safe operation of the switch mode power converter during the fault condition.
Claims21
A device comprising:
- an adaptive gate driver for a switch mode power converter controller, the adaptive driver configured to drive a power transistor of the switch mode power converter with first gate drive pulses in a normal range of operating conditions, the first gate drive pulses each allowing a saturation region drain current through the power transistor to exceed a safe operating area of the power transistor during a fault condition, the adaptive gate driver comprising:
- an input to be coupled to receive a signal indicative of a fault condition;
- and
- control logic coupled to respond to an indication of the fault condition by adapting the driving of the power transistor so that the power transistor is driven with a second gate drive pulse with reduced strength;
- the second gate drive pulse having at least one of:
- a lower voltage than the first gate drive pulses, and
- a lower current than the first gate drive pulses;
- so that a saturation region drain current through the power transistor remains within the safe operating area of the power switch.
A switch mode power converter including:
- an adaptive gate driver circuit coupled to output a drive signal to control a power transistor;
- and
- a control logic circuit coupled to control the adaptive gate driver circuit, wherein the control logic circuit is operable to cause the adaptive gate driver circuit to output the drive signal with a first drive current while the control logic circuit is operating in a normal mode of operation, and wherein the control logic circuit is operable to cause the driver circuit to output the drive signal with a second drive current that is less than the first drive current while the control logic circuit is operating in an SOA mode of operation in response to detecting a fault condition.
Dependencies are inferred from the claim text.