RRAM device

An integrated circuit device, comprising:

• a substrate comprising a transistor with a source region and a drain region;
• a lower metal interconnect layer disposed over the substrate and electrically coupled to the drain region of the transistor through a series of contacts and vias;
• a resistive random access memory (RRAM) cell disposed over the lower metal interconnect layer and comprising a bottom electrode, a RRAM dielectric arranged over the bottom electrode, and a top electrode arranged over the RRAM dielectric;
• and
• an upper metal interconnect layer disposed over the RRAM cell and electrically coupled to the top electrode of the RRAM cell through a via;
• wherein the bottom electrode comprises an upper portion with a trapezoid shape and a lower portion with a smaller lateral dimension than the upper portion;
• wherein the top electrode has a cuboid shape with a lateral dimension smaller than a minimum lateral dimension of the upper portion of the bottom electrode.

A method of forming an integrated circuit device, comprising:

• forming a bottom electrode layer over a substrate, a RRAM dielectric layer over the bottom electrode layer, and a top electrode layer over the RRAM dielectric layer;
• patterning the top electrode layer to form a top electrode;
• depositing a sidewall polymer mask along a sidewall of the top electrode;
• and
• patterning the bottom electrode layer according to the sidewall polymer mask to form a bottom electrode having a sidewall that is inwardly tilted;
• wherein the bottom electrode is formed by forming a via opening through a bottom dielectric layer followed by forming the bottom electrode layer into the via opening and over the bottom dielectric layer, such that the bottom electrode is formed to comprise a lower portion surrounded by the bottom dielectric layer and an upper portion that is wider than the lower portion.