Contact resistance reduction technique
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChun Hsiung Tsai, Ming-Te Chen
Life of this patent
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Abstract
An embodiment is a method of manufacturing a semiconductor device, the method including forming a first gate over a substrate, forming a recess in the substrate adjacent the first gate, epitaxially forming a strained material stack in the recess, the strained material stack comprising at least three layers, each of the at least three layers comprising a dopant. The method further includes co-implanting the strained material stack with dopants comprising boron, germanium, indium, tin, or a combination thereof, forming a metal layer on the strained material stack, and annealing the metal layer and the strained material stack forming a metal-silicide layer.
Claims20
A method of manufacturing a semiconductor device, the method comprising:
- providing a substrate having a semiconductor fin extending from the substrate;
- forming a first gate structure over the semiconductor fin;
- forming a recess in the semiconductor fin adjacent the first gate structure;
- epitaxially forming a strained material stack in the recess, the strained material stack comprising at least three sequentially and selectively grown layers, each of the at least three sequentially and selectively grown layers comprising a first dopant, each of the at least three sequentially and selectively grown layers having a dopant concentration;
- increasing the dopant concentration of a first subset of the at least three sequentially and selectively grown layers, the increasing comprising co-implanting the first subset of the strained material stack with second dopants comprising boron, germanium, indium, tin, or a combination thereof;
- forming a metal layer on the strained material stack;
- and
- locally annealing the metal layer and the strained material stack at a higher temperature than the substrate and the first gate structure to form a metal-silicide layer.
A method of forming a Fin Field-Effect Transistor (FinFET), the method comprising:
- forming a plurality of fins extending from a substrate;
- forming a dummy gate structure over the plurality of fins;
- forming recesses in the plurality of fins adjacent the dummy gate structure;
- epitaxially forming a plurality of strained material stacks in the recesses in the plurality of fins, each of the strained material stacks comprising an epitaxially grown germanium-tin (GeSn) layer and a plurality of epitaxially grown boron-doped (B-doped) silicon-germanium (SiGeB) layers, the epitaxially grown GeSn layer interposed between the plurality of epitaxially grown SiGeB layers;
- implanting the strained material stacks with B, indium (In), Sn, or a combination thereof;
- forming a metal layer on the strained material stacks;
- annealing the metal layer and the strained material stacks to form metal-silicide layers on the strained material stacks, wherein the annealing comprises locally increasing a temperature of the metal layer and the strained material stacks to a higher temperature than a temperature of the substrate, wherein the temperature of the metal layer and the strained material stacks is locally increased by performing a microwave anneal (MWA) process on the metal layer and the strained material stacks;
- and
- forming a metal contact to the strained material stacks, the metal contact contacting the metal-silicide layers.
A method of forming a Fin Field-Effect Transistor (FinFET), the method comprising:
- forming a plurality of fins extending from a substrate;
- forming a first gate structure over the plurality of fins;
- forming recesses in the plurality of fins adjacent the first gate structure;
- epitaxially forming a plurality of strained material stacks in the recesses in the plurality of fins, the strained material stacks comprising a plurality of epitaxial layers, the plurality of epitaxial layers including a first epitaxially grown tin-doped (Sn-doped) layer interposed between two or more epitaxially grown boron-doped (B-doped) layers;
- co-implanting the strained material stacks with boron (B), indium (In), tin (Sn), antimony (Sb), or a combination thereof, the co-implanting increasing doping concentrations of each of the plurality of epitaxial layers;
- depositing a metal layer on the strained material stacks;
- and
- heating the metal layer and the strained material stacks to a first temperature while heating the substrate to a second temperature, the first temperature greater than the second temperature, wherein heating the metal layer and the strained material stacks forms metal-silicide layers on the strained material stacks.
Dependencies are inferred from the claim text.