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US 9,543,437 B2Granted
Integrated circuit with dual stress liner boundary
AssigneeTexas Instruments Incorporated
InventorsYoun Sung Choi, Greg Charles Baldwin
Life of this patent
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Abstract
An integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell.
Claims7
An integrated circuit, comprising:
- a substrate including:
- an nwell surrounded by an nwell perimeter;
- a p-active region in the nwell;
- and
- an n-active region outside of the nwell;
- and
- a tensile contact etch stop layer formed over the n-active region and patterned with an opening defined by:
- a perpendicular stress liner border aligned substantially within the nwell parameter;
- and
- a parallel stress liner border aligned between the p-active region and n-active region and outside of the nwell perimeter.
7 more elements
Dependencies are inferred from the claim text.