Method and structure of making enhanced UTBB FDSOI devices
AssigneesSTMicroelectronics S.r.l., STMicroelectronics (Crolles 2) SAS
InventorsQing Liu, Thomas Skotnicki
Life of this patent
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Abstract
An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material.
Claims21
A method of forming a transistor, the method comprising:
- exposing a sidewall and a portion of a bottom surface of a first layer of semiconductor material by etching a trench and a first recess in a first layer of dielectric material that is below the first layer of semiconductor material;
- forming a gate dielectric on the sidewall, on the portion of the bottom surface, and on a top surface of the first layer of semiconductor material;
- and
- forming a gate electrode on the gate dielectric on the sidewall, on the portion of the bottom surface, and on the top surface of the first layer of semiconductor material.
A method, comprising:
- forming a layer of semiconductor material on a first layer of dielectric material, the layer of semiconductor material having a top surface, side surfaces, and a bottom surface;
- forming a recess between the first layer of dielectric material and the layer of semiconductor material by removing a first portion of the first layer of dielectric material supporting the bottom surface of the layer of semiconductor material, a second portion of the first layer of dielectric material remaining in contact with the bottom surface of the layer of semiconductor material;
- forming a transistor, the forming of the transistor including:
- forming a gate dielectric on the top surface, the side surfaces, and on a portion of the bottom surface of the layer of semiconductor material and in the recess between the first layer of dielectric material and the layer of semiconductor material;
- and
- forming a gate electrode on the gate dielectric on the top surface, the side surfaces, and on the portion of the bottom surface of the layer of semiconductor material.
A method, comprising:
- forming a transistor structure, the forming including:
- forming a first region of semiconductor material by:
- forming a first layer of semiconductor material;
- and
- removing portions of the first layer of semiconductor material to expose a top surface, side surfaces, and first portions of a bottom surface of the first layer of semiconductor material, second portions of the bottom surface remaining unexposed;
- forming a second layer of semiconductor material on the top and side surfaces of the first region of semiconductor material;
- forming a gate dielectric on the top surface, on the portion of the bottom surface, and on the side surfaces of the first region of semiconductor material;
- forming a gate electrode on the gate dielectric on the top surface, on the portion of the bottom surface, and on the side surfaces of the first region of semiconductor material;
- forming a source region of the transistor in the second layer of semiconductor material;
- and
- forming a drain region of the transistor in the second layer of semiconductor material.
A method, comprising:
- forming a transistor structure, the forming of the transistor structure including:
- forming a semiconductor region on a buried oxide layer;
- separating a first portion of the buried oxide layer from the semiconductor region by a first space by removing a second portion of the buried oxide layer between an outer portion of a bottom surface of the semiconductor region and the first portion of the buried oxide layer, a central portion of the bottom surface of the semiconductor region remaining in contact with the buried oxide layer;
- and
- forming a gate electrode on the semiconductor region, on the buried oxide layer, and in the first space.
A method, comprising:
- forming a transistor structure, the forming of the transistor structure including:
- forming a first semiconductor region on a buried oxide layer;
- separating a first portion of the buried oxide layer from the first semiconductor region by a first space;
- forming a gate electrode on the first semiconductor region, on the buried oxide layer, and in the first space, wherein forming the transistor structure includes separating a second portion of the buried oxide layer from the first semiconductor region by a second space and forming the gate electrode in the second space.
The method of 20 wherein forming the transistor structure includes forming source and drain regions in a second semiconductor region on the first semiconductor region.
Dependencies are inferred from the claim text.