US 9,543,426 B2Granted

Semiconductor devices with self-aligned contacts and low-k spacers

AssigneesGlobalfoundries Inc., International Business Machines Corporation

InventorsRuilong Xie, Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz

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Abstract

One illustrative method disclosed herein includes removing a portion of a sacrificial sidewall spacer to thereby expose at least a portion of the sidewalls of a sacrificial gate electrode and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode. In this example, the method also includes forming a sacrificial gap fill material above the liner layer, exposing and removing the sacrificial gate electrode to thereby define a gate cavity that is laterally defined by the liner layer, forming a replacement gate structure, removing the sacrificial gap fill material and forming a low-k sidewall spacer adjacent the liner layer. A device is also disclosed that includes a gate cap layer, a layer of silicon nitride or silicon oxynitride positioned on each of two upstanding portions of a gate insulation layer and a low-k sidewall spacer positioned on the layer of silicon nitride or silicon oxynitride.

Claims21

Dependent claims

A device, comprising:

a gate structure positioned above a semiconducting substrate, said gate structure comprising a gate insulation layer and a gate electrode, said gate insulation layer having two upstanding portions that are substantially vertically oriented relative to an upper surface of said substrate;
raised source/drain regions positioned laterally adjacent to opposing sides of said gate structure;
a first sidewall spacer positioned between said gate structure and said raised source/drain regions, wherein said first sidewall spacer is positioned on and in contact with a lower sidewall surface of each of said two upstanding portions of said gate insulation layer;
a liner layer comprising one of silicon nitride and silicon oxynitride, wherein said liner layer comprises a first liner layer portion positioned on and in contact with an upper sidewall surface of each of said two upstanding portions of said gate insulation layer and a second liner layer portion positioned laterally adjacent a sidewall surface of each of said raised source/drain regions, each of said first and second liner layer portions having a lower surface that is in direct contact with an upper surface of said first sidewall spacer, wherein said two respective upstanding portions are positioned between and separate said first liner layer portions and respective sidewall surfaces of said gate electrode;
and
a low-k sidewall spacer positioned on said liner layer, wherein a portion of said low-k sidewall spacer is positioned between and separates said first and second liner layer portions and is in direct contact with said upper surface of said first sidewall spacer.

3 more elements

A device, comprising:

a gate structure positioned above a semiconducting substrate, said gate structure comprising a gate insulation layer and a gate electrode, said gate insulation layer having first and second upstanding portions;
raised source/drain regions positioned laterally adjacent to opposing sides of said gate structure;
a first sidewall spacer positioned between said gate structure and said raised source/drain regions, wherein said first sidewall spacer is positioned on and in contact with a lower portion of an outer sidewall surface of each of said first and second upstanding portions of said gate insulation layer;
a gate cap layer positioned above said gate insulation layer and said gate electrode, said gate cap layer having first and second sidewalls;
a first layer of material and a second layer of material positioned on and in contact with an upper portion of said outer sidewall surface of said first upstanding portion and said second upstanding portion, respectively, of said gate insulation layer, said first layer of material and said second layer of material each comprising a first layer portion contacting said first sidewall and said second sidewall, respectively, of said gate cap layer and a second layer portion contacting a sidewall portion of a respective one of said raised source/drain regions, wherein said first and second layer portions of said first layer of material and said second layer of material each have a lower surface that is in direct contact with an upper surface of said first sidewall spacer and wherein said first upstanding portion is positioned between and separates said first layer portion of said first layer of material and a first sidewall surface of said gate electrode and said second upstanding portion is positioned between and separates said first layer portion of said second layer of material and a second sidewall surface of said gate electrode;
and
first and second low-k sidewall spacers positioned on and in contact with said first and second layers of material, respectively, wherein a portion of each of said first and second low-k sidewall spacers is positioned between and separates said first and second layer portions of each of said first and second layers of material and is in direct contact with said upper surface of said first sidewall spacer.

4 more elements

A device, comprising:

a gate structure positioned above a semiconducting substrate, said gate structure comprising a high-k gate insulation layer and a gate electrode comprised of at least one layer of metal, said gate insulation layer having first and second upstanding portions that are substantially vertically oriented relative to an upper surface of said substrate;
raised source/drain regions positioned laterally adjacent to opposing sides of said gate structure;
a first sidewall spacer positioned between said gate structure and said raised source/drain regions, said first sidewall spacer being positioned on and in contact with a lower portion of an outer sidewall surface of each of said first and second upstanding portions of said gate insulation layer and a sidewall of each of said raised source/drain regions;
a gate cap layer positioned above said gate insulation layer and said gate electrode;
a first layer of material and a second layer of material, each comprising a first portion positioned on and in contact with an upper portion of said outer sidewall surface of said first upstanding portion and said second upstanding portion, respectively, of said gate insulation layer and a second portion positioned on and in contact with said sidewall of a respective one of said raised source/drain regions, wherein said first upstanding portion is positioned between and separates said first portion of said first layer of material and a first sidewall surface of said gate electrode and said second upstanding portion is positioned between and separates said first portion of said second layer of material and a second sidewall surface of said gate electrode, each of said first and second portions of said first and second layers of material comprising one of silicon nitride or silicon oxynitride and having a lower surface that is in direct contact with an upper surface of said first sidewall spacer;
and
first and second low-k sidewall spacers positioned on and in contact with said first and second layers of material, respectively, wherein a portion of each of said first and second low-k sidewall spacers is positioned between and separates said first and second portions of each of said first and second layers of material and is in direct contact with said upper surface of said first sidewall spacer.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/957,587Filed 2 Aug 2013 · division
Priority: 13 Aug 2012
Published: US 2014/0042502 A113 Feb 2014
Granted: 10 Jan 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10D 30/60
Field-effect transistors [FET]: insulated-gate field-effect transistors [IGFET]
H10D 64/015
Manufacture or treatment: removing at least parts of gate spacers, e.g. disposable spacers
H10D 30/0275
Of lateral single-gate IGFETs: forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised…
H10D 62/021
Manufacture or treatment: forming source or drain recesses by etching e.g. recessing by etching and then refilling