Method of manufacturing a reduced free-charge carrier lifetime semiconductor structure

A method of manufacturing a power semiconductor device, the method comprising:

• providing a semiconductor substrate;
• forming a transistor gate structure in a trench arranged in the semiconductor substrate;
• forming a body region of a first conductivity type adjacent the transistor gate structure;
• forming a first highly-doped region of a second conductivity type in an upper portion of the body region;
• forming a drift zone of the second conductivity type below the body region;
• forming a second highly-doped region of the second conductivity type below the drift zone;
• forming an insulator layer along the semiconductor substrate;
• forming an opening in the insulator layer such that the insulator layer covers the transistor gate structure and exposes a region of the substrate that is adjacent to the transistor gate structure, and
• forming an end-of-range irradiation region adjacent the transistor gate structure by irradiating the semiconductor substrate, the end-of-range irradiation region having a plurality of vacancies,
• wherein the insulator layer is used as a mask for irradiating the semiconductor substrate such that irradiated particles pass through the opening formed in the insulating layer but are prevented by the insulator layer from damaging gate insulators disposed on inner walls of the trenches, and
• wherein the opening in the insulator layer is formed such that sidewalk of the opening form an oblique angle with an upper surface of the substrate, and wherein forming the end-of-range irradiation region comprises passing the irradiated particles through the sidewalls of the region such that the end-of-range irradiation region forms a well-shaped region within the semiconductor substrate, wherein the well-shaped region comprises sidewalls that are parallel to the sidewalls of the opening and directly adjoin outer walls of the gate trenches.

A method of manufacturing a reduced free-charge carrier lifetime semiconductor structure, the method comprising:

• forming a plurality of transistor gate structures in trenches arranged in a semiconductor substrate;
• forming a body region between adjacent ones of the transistor gate structures;
• and
• forming an insulator layer along the semiconductor substrate;
• forming an opening in the insulator layer such that the insulator layer covers adjacent ones of the transistor gate structures and exposes a region of the substrate that is between the adjacent ones of the transistor gate structures;
• forming an end-of-range irradiation region between the adjacent ones of the transistor gate structures by irradiating the semiconductor substrate, the end-of-range irradiation region having a plurality of vacancies,
• wherein only the insulator layer is used as a mask for irradiating the semiconductor substrate such that irradiated particles pass through the opening formed in the insulating layer but are prevented by the insulator layer from damaging gate insulators disposed on inner walls of the trenches, and
• wherein the irradiated particles directly contact an exposed outer surface of the insulator layer mask during formation of the end-of-range irradiation region.