US 9,543,401 B2 · 3D semiconductor integrated circuit device and method of manufacturing the same

Abstract

A 3D semiconductor integrated circuit device and a method of manufacturing the same are provided. An active pillar is formed on a semiconductor substrate, and an interlayer insulating layer is formed so that the active pillar is buried in the interlayer insulating layer. The interlayer insulating layer is etched to form a hole so that the active pillar and a peripheral region of the active pillar are exposed. An etching process is performed on the peripheral region of the active pillar exposed through the hole by a certain depth, and a space having the depth is provided between the active pillar and the interlayer insulating layer. A silicon material layer is formed to be buried in the space having the depth, and an ohmic contact layer is formed on the silicon material layer and the active pillar.

Claims24

Dependent claims

A method of manufacturing a semiconductor integrated circuit device, the method comprising:

forming an active pillar in a semiconductor substrate;
forming a gate electrode to surround sidewall of the active pillar;
forming an interlayer insulating layer over the semiconductor substrate and the active pillar;
forming a hole by etching the interlayer insulating layer so that an upper surface of the active pillar is exposed by the hole;
forming a space extending from the hole down to between an upper sidewall of the active pillar and the interlayer insulating layer so that the upper sidewall of the active pillar is exposed and an upper surface of the gate electrode is not exposed;
forming a silicon material layer in the space;
and
forming an ohmic contact layer on the silicon material layer and on the active pillar in the hole.

5 more elements

A method of manufacturing a semiconductor integrated circuit device, the method comprising:

providing active pillars in a semiconductor substrate;
providing a stack of a gate insulating layer and a gate electrode over a lower sidewall of each of the active pillars;
providing an interlayer insulating layer extending over the active pillars to fill with a first space between the active pillars;
forming a hole by etching the interlayer insulating layer so that the hole exposes an upper surface of each of the active pillars and the gate insulating layer;
etching the exposed gate insulating layer by a given depth to form a second space extending from the hole to between the interlayer insulating layer and an upper sidewall of each of the active pillars, wherein the gate electrode is not exposed by the second space;
forming a silicon material layer in the second space;
forming an ohmic contact layer on the silicon material layer and on the active pillars in the hole;
and
sequentially forming a lower electrode and a variable resistance material layer over the ohmic contact layer,
wherein the lower electrode is formed in the hole.

7 more elements

Dependencies are inferred from the claim text.

3D semiconductor integrated circuit device and method of manufacturing the same

Life of this patent

3D semiconductor integrated circuit device and method of manufacturing the same

Life of this patent

Abstract

Claims24