Semiconductor package
AssigneeSK hynix Inc.
InventorsHan Jun Bae, Won Duck Jung
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a substrate, an elastic buffer layer disposed on a surface of the substrate, wiring patterns disposed on a first surface of the elastic buffer layer, and a semiconductor chip disposed on a second surface of the elastic buffer layer facing away from the first surface of the elastic buffer layer. The semiconductor chip includes trenches formed on a surface facing the elastic buffer layer. Interconnection members are disposed to electrically connect the elastic buffer layer to the substrate. Each of the interconnection members has one end electrically connected to one of the wiring patterns and the other end electrically connected to the substrate.
Claims19
A semiconductor package comprising:
- a substrate having a first surface and a second surface facing away from the first surface;
- an elastic buffer layer disposed over the first surface of the substrate;
- wiring patterns disposed on a first surface of the elastic buffer layer;
- a semiconductor chip disposed on a second surface of the elastic buffer layer facing away from the first surface of the elastic buffer layer, wherein the semiconductor chip includes trenches formed on a surface facing the elastic buffer layer, wherein the elastic buffer layer crosses each trench to provide a respective cavity;
- and
- interconnection members electrically connecting the wiring patterns to the substrate,
- wherein each of the interconnection members has one end electrically connected to one of the wiring patterns and the other end electrically connected to the substrate.
A semiconductor package comprising:
- a semiconductor chip (400) having a front-side portion (400a) and a back-side portion (400b) facing away from the front-side portion ;
- a substrate (300) disposed under the front-side portion of the semiconductor chip;
- an insulation layer (420) formed on the front-side portion of the semiconductor chip, wherein the insulation layer includes trenches (431) disposed therein and the trenches have a predetermined depth;
- an elastic buffer layer (445) disposed between the insulation layer and the substrate, wherein the elastic buffer layer crosses each trench to provide a respective cavity (S3);
- lower wiring patterns (415) disposed in the elastic buffer layer, wherein each of the lower wiring patterns includes a landing pad (272) aligned with one of the trenches;
- and
- interconnection members (312) electrically connecting the landing pads to the substrate,
- wherein each of the interconnection members has one end electrically connected to one of the landing pads and the other end electrically connected to the substrate.
A semiconductor package comprising:
- a first substrate (200) having a first surface (200a) and a second surface (200b) facing away from the first surface;
- and
- a second substrate (231) disposed over the first surface of the first substrate and haying:
- a substrate core (230) having a first surface and a second surface facing away from the first surface, wherein a trench (232a) is disposed in the substrate core to be adjacent to the second surface;
- an elastic buffer layer (220) disposed on the second surface of the substrate core and having an opening (220a) disposed on its surface facing the first substrate, wherein the elastic buffer layer crosses the trench to provide a cavity (S2);
- and
- a lower wiring pattern (250) disposed inside the elastic buffer layer and having a landing pad (272) disposed to be aligned to the trench;
- and
- an interconnection member (210) electrically connecting the first substrate to the second substrate, wherein one end of the interconnection member is connected to the lower wiring pattern and the other end is connected to the first substrate.
Dependencies are inferred from the claim text.